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AMDGPU: Make VReg_1 size be 1
This was getting chosen as the preferred 32-bit register class based on how TableGen selects subregister classes. llvm-svn: 371438
1 parent d60ff75 commit 8bc05d7

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6 files changed

+35
-23
lines changed

6 files changed

+35
-23
lines changed

‎llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -489,6 +489,15 @@ bool SILowerI1Copies::runOnMachineFunction(MachineFunction &TheMF) {
489489
return true;
490490
}
491491

492+
#ifndef NDEBUG
493+
static bool isVRegCompatibleReg(const SIRegisterInfo &TRI,
494+
const MachineRegisterInfo &MRI,
495+
Register Reg) {
496+
unsigned Size = TRI.getRegSizeInBits(Reg, MRI);
497+
return Size == 1 || Size == 32;
498+
}
499+
#endif
500+
492501
void SILowerI1Copies::lowerCopiesFromI1() {
493502
SmallVector<MachineInstr *, 4> DeadCopies;
494503

@@ -509,7 +518,7 @@ void SILowerI1Copies::lowerCopiesFromI1() {
509518
LLVM_DEBUG(dbgs() << "Lower copy from i1: " << MI);
510519
DebugLoc DL = MI.getDebugLoc();
511520

512-
assert(TII->getRegisterInfo().getRegSizeInBits(DstReg, *MRI) == 32);
521+
assert(isVRegCompatibleReg(TII->getRegisterInfo(), *MRI, DstReg));
513522
assert(!MI.getOperand(0).getSubReg());
514523

515524
ConstrainRegs.insert(SrcReg);

‎llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1438,8 +1438,6 @@ const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
14381438
// TargetRegisterClass to mark which classes are VGPRs to make this trivial.
14391439
bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
14401440
unsigned Size = getRegSizeInBits(*RC);
1441-
if (Size < 32)
1442-
return false;
14431441
switch (Size) {
14441442
case 32:
14451443
return getCommonSubClass(&AMDGPU::VGPR_32RegClass, RC) != nullptr;
@@ -1457,8 +1455,11 @@ bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
14571455
return getCommonSubClass(&AMDGPU::VReg_512RegClass, RC) != nullptr;
14581456
case 1024:
14591457
return getCommonSubClass(&AMDGPU::VReg_1024RegClass, RC) != nullptr;
1458+
case 1:
1459+
return getCommonSubClass(&AMDGPU::VReg_1RegClass, RC) != nullptr;
14601460
default:
1461-
llvm_unreachable("Invalid register class size");
1461+
assert(Size < 32 && "Invalid register class size");
1462+
return false;
14621463
}
14631464
}
14641465

@@ -1506,6 +1507,8 @@ const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass(
15061507
return &AMDGPU::VReg_512RegClass;
15071508
case 1024:
15081509
return &AMDGPU::VReg_1024RegClass;
1510+
case 1:
1511+
return &AMDGPU::VReg_1RegClass;
15091512
default:
15101513
llvm_unreachable("Invalid register class size");
15111514
}

‎llvm/lib/Target/AMDGPU/SIRegisterInfo.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -682,7 +682,7 @@ def AReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32,
682682
}
683683

684684
def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)> {
685-
let Size = 32;
685+
let Size = 1;
686686
}
687687

688688
def VS_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,

‎llvm/test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@ body: |
6969
%25:vgpr_32 = V_AND_B32_e32 target-flags(amdgpu-gotprel32-hi) 1, %10.sub2, implicit $exec
7070
%26:sreg_64 = V_CMP_EQ_U32_e64 1, %25, implicit $exec
7171
%27:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
72-
%28:vreg_1 = COPY %27
72+
%28:vgpr_32 = COPY %27
7373
%29:sreg_64 = COPY $exec, implicit-def $exec
7474
%30:sreg_64 = S_AND_B64 %29, %26, implicit-def dead $scc
7575
$exec = S_MOV_B64_term %30
@@ -81,7 +81,7 @@ body: |
8181
%31:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN undef %32:vgpr_32, undef %33:sreg_128, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from constant-pool, align 1, addrspace 4)
8282
%34:sreg_64_xexec = V_CMP_NE_U32_e64 0, %31, implicit $exec
8383
%35:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, -1, %34, implicit $exec
84-
%28:vreg_1 = COPY %35
84+
%28:vgpr_32 = COPY %35
8585
S_BRANCH %bb.10
8686
8787
bb.9:
@@ -91,7 +91,7 @@ body: |
9191
bb.10:
9292
successors: %bb.9
9393
$exec = S_OR_B64 $exec, %29, implicit-def $scc
94-
%36:vreg_1 = COPY %28
94+
%36:vgpr_32 = COPY %28
9595
%37:sreg_64_xexec = V_CMP_NE_U32_e64 0, %36, implicit $exec
9696
%38:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %37, implicit $exec
9797
%39:vgpr_32 = V_MOV_B32_e32 0, implicit $exec

‎llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -84,8 +84,8 @@ body: |
8484
%38:vreg_128 = IMPLICIT_DEF
8585
%39:vreg_128 = IMPLICIT_DEF
8686
%40:vgpr_32 = IMPLICIT_DEF
87-
%41:vreg_1 = COPY killed %35
88-
%42:vreg_1 = COPY killed %34
87+
%41:vgpr_32 = COPY killed %35
88+
%42:vgpr_32 = COPY killed %34
8989
%43:sreg_64 = COPY $exec, implicit-def $exec
9090
%44:sreg_64 = S_AND_B64 %43, %30, implicit-def dead $scc
9191
%45:sreg_64 = S_XOR_B64 %44, %43, implicit-def dead $scc
@@ -96,7 +96,7 @@ body: |
9696
bb.5:
9797
successors: %bb.9(0x80000000)
9898
$exec = S_OR_B64 $exec, %46, implicit-def $scc
99-
%47:vreg_1 = COPY killed %48
99+
%47:vgpr_32 = COPY killed %48
100100
%49:vgpr_32 = COPY killed %50
101101
%51:vreg_128 = COPY killed %52
102102
%53:vreg_128 = COPY killed %54
@@ -109,16 +109,16 @@ body: |
109109
%38:vreg_128 = COPY killed %59
110110
%39:vreg_128 = COPY killed %51
111111
%40:vgpr_32 = COPY killed %49
112-
%41:vreg_1 = COPY killed %47
113-
%42:vreg_1 = COPY killed %58
112+
%41:vgpr_32 = COPY killed %47
113+
%42:vgpr_32 = COPY killed %58
114114
S_BRANCH %bb.9
115115
116116
bb.6:
117117
successors: %bb.7(0x40000000), %bb.13(0x40000000)
118118
$exec = S_OR_B64 $exec, killed %60, implicit-def $scc
119119
%61:sreg_64 = V_CMP_NE_U32_e64 0, killed %62, implicit $exec
120120
%63:vreg_128 = COPY killed %64
121-
%65:vreg_1 = COPY killed %66
121+
%65:vgpr_32 = COPY killed %66
122122
%67:sreg_64 = COPY $exec, implicit-def $exec
123123
%68:sreg_64 = S_AND_B64 %67, %61, implicit-def dead $scc
124124
$exec = S_MOV_B64_term killed %68
@@ -130,7 +130,7 @@ body: |
130130
%69:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
131131
%70:vreg_128 = COPY killed %33
132132
%63:vreg_128 = COPY killed %70
133-
%65:vreg_1 = COPY killed %69
133+
%65:vgpr_32 = COPY killed %69
134134
S_BRANCH %bb.13
135135
136136
bb.8:
@@ -145,8 +145,8 @@ body: |
145145
bb.9:
146146
successors: %bb.6(0x04000000), %bb.4(0x7c000000)
147147
$exec = S_OR_B64 $exec, %45, implicit-def $scc
148-
%62:vreg_1 = COPY killed %42
149-
%66:vreg_1 = COPY killed %41
148+
%62:vgpr_32 = COPY killed %42
149+
%66:vgpr_32 = COPY killed %41
150150
%76:vgpr_32 = COPY killed %40
151151
%77:vreg_128 = COPY killed %39
152152
%64:vreg_128 = COPY killed %38
@@ -193,7 +193,7 @@ body: |
193193
%54:vreg_128 = COPY killed %23
194194
%52:vreg_128 = IMPLICIT_DEF
195195
%50:vgpr_32 = IMPLICIT_DEF
196-
%48:vreg_1 = COPY killed %88
196+
%48:vgpr_32 = COPY killed %88
197197
%89:sreg_64 = COPY $exec, implicit-def $exec
198198
%90:sreg_64 = S_AND_B64 %89, %87, implicit-def dead $scc
199199
%46:sreg_64 = S_XOR_B64 %90, %89, implicit-def dead $scc
@@ -204,7 +204,7 @@ body: |
204204
bb.13:
205205
successors: %bb.14(0x40000000), %bb.16(0x40000000)
206206
$exec = S_OR_B64 $exec, killed %67, implicit-def $scc
207-
%91:vreg_1 = COPY killed %65
207+
%91:vgpr_32 = COPY killed %65
208208
%92:vreg_128 = COPY killed %63
209209
%93:sreg_64 = V_CMP_NE_U32_e64 0, killed %91, implicit $exec
210210
%94:vreg_128 = COPY killed %78
@@ -231,7 +231,7 @@ body: |
231231
%54:vreg_128 = COPY killed %101
232232
%52:vreg_128 = COPY %59
233233
%50:vgpr_32 = COPY killed %102
234-
%48:vreg_1 = COPY killed %98
234+
%48:vgpr_32 = COPY killed %98
235235
S_BRANCH %bb.5
236236
237237
bb.16:

‎llvm/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,7 @@ body: |
6060
bb.3:
6161
successors: %bb.6(0x80000000)
6262
%15:vreg_128 = IMPLICIT_DEF
63-
%16:vreg_1 = COPY killed %14
63+
%16:vgpr_32 = COPY killed %14
6464
S_BRANCH %bb.6
6565
6666
bb.4:
@@ -83,7 +83,7 @@ body: |
8383
8484
bb.6:
8585
successors: %bb.8(0x40000000), %bb.10(0x40000000)
86-
%25:vreg_1 = COPY killed %16
86+
%25:vgpr_32 = COPY killed %16
8787
%26:vreg_128 = COPY killed %15
8888
%27:sreg_64 = V_CMP_NE_U32_e64 0, killed %25, implicit $exec
8989
%28:sreg_64 = S_AND_B64 $exec, killed %27, implicit-def dead $scc
@@ -97,7 +97,7 @@ body: |
9797
$exec = S_OR_B64 $exec, killed %23, implicit-def $scc
9898
%30:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
9999
%15:vreg_128 = COPY %13
100-
%16:vreg_1 = COPY killed %30
100+
%16:vgpr_32 = COPY killed %30
101101
S_BRANCH %bb.6
102102
103103
bb.8:

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