@@ -88,7 +88,7 @@ def Vector_ContractionOp :
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iterator in the iterator type list, to each dimension of an N-D vector.
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Examples:
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-
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+ ```mlir
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// Simple dot product (K = 0).
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#contraction_accesses = [
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affine_map<(i) -> (i)>,
@@ -139,6 +139,7 @@ def Vector_ContractionOp :
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%5 = vector.contract #contraction_trait %0, %1, %2, %lhs_mask, %rhs_mask
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: vector<7x8x16x15xf32>, vector<8x16x7x5xf32> into vector<8x15x8x5xf32>
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+ ```
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}];
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let builders = [OpBuilder<
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"Builder *builder, OperationState &result, Value lhs, Value rhs, "
@@ -203,7 +204,7 @@ def Vector_ReductionOp :
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http://llvm.org/docs/LangRef.html#experimental-vector-reduction-intrinsics
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Examples:
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- ```
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+ ```mlir
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%1 = vector.reduction "add", %0 : vector<16xf32> into f32
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%3 = vector.reduction "xor", %2 : vector<4xi32> into i32
@@ -247,7 +248,7 @@ def Vector_BroadcastOp :
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shaped vector with the same element type is always legal.
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Examples:
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- ```
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+ ```mlir
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%0 = constant 0.0 : f32
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%1 = vector.broadcast %0 : f32 to vector<16xf32>
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%2 = vector.broadcast %1 : vector<16xf32> to vector<4x16xf32>
@@ -290,7 +291,7 @@ def Vector_ShuffleOp :
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above, all mask values are in the range [0,s_1+t_1)
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Examples:
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- ```
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+ ```mlir
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%0 = vector.shuffle %a, %b[0, 3]
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: vector<2xf32>, vector<2xf32> ; yields vector<2xf32>
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%1 = vector.shuffle %c, %b[0, 1, 2]
@@ -332,7 +333,7 @@ def Vector_ExtractElementOp :
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https://llvm.org/docs/LangRef.html#extractelement-instruction
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Example:
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- ```
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+ ```mlir
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%c = constant 15 : i32
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%1 = vector.extractelement %0[%c : i32]: vector<16xf32>
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```
@@ -360,7 +361,7 @@ def Vector_ExtractOp :
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the proper position. Degenerates to an element type in the 0-D case.
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Examples:
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- ```
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+ ```mlir
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%1 = vector.extract %0[3]: vector<4x8x16xf32>
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%2 = vector.extract %0[3, 3, 3]: vector<4x8x16xf32>
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```
@@ -396,7 +397,7 @@ def Vector_ExtractSlicesOp :
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Currently, only unit strides are supported.
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Examples:
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- ```
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+ ```mlir
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%0 = vector.transfer_read ...: vector<4x2xf32>
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%1 = vector.extract_slices %0, [2, 2], [1, 1]
@@ -448,8 +449,7 @@ def Vector_FMAOp :
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to the `llvm.fma.*` intrinsic.
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Example:
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-
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- ```
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+ ```mlir
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%3 = vector.fma %0, %1, %2: vector<8x16xf32>
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```
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}];
@@ -483,7 +483,7 @@ def Vector_InsertElementOp :
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https://llvm.org/docs/LangRef.html#insertelement-instruction
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Example:
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- ```
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+ ```mlir
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%c = constant 15 : i32
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%f = constant 0.0f : f32
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%1 = vector.insertelement %f, %0[%c : i32]: vector<16xf32>
@@ -516,7 +516,7 @@ def Vector_InsertOp :
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position. Degenerates to a scalar source type when n = 0.
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Examples:
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- ```
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+ ```mlir
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%2 = vector.insert %0, %1[3]:
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vector<8x16xf32> into vector<4x8x16xf32>
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%5 = vector.insert %3, %4[3, 3, 3]:
@@ -559,7 +559,7 @@ def Vector_InsertSlicesOp :
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Currently, only unit strides are supported.
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Examples:
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- ```
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+ ```mlir
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%0 = vector.extract_slices %0, [2, 2], [1, 1]
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: vector<4x2xf32> into tuple<vector<2x2xf32>, vector<2x2xf32>>
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@@ -617,7 +617,7 @@ def Vector_InsertStridedSliceOp :
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the proper location as specified by the offsets.
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Examples:
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- ```
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+ ```mlir
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%2 = vector.insert_strided_slice %0, %1
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{offsets = [0, 0, 2], strides = [1, 1]}:
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vector<2x4xf32> into vector<16x4x8xf32>
@@ -659,8 +659,7 @@ def Vector_OuterProductOp :
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lower to actual `fma` instructions on x86.
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Examples:
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-
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- ```
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+ ```mlir
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%2 = vector.outerproduct %0, %1: vector<4xf32>, vector<8xf32>
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return %2: vector<4x8xf32>
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@@ -709,8 +708,8 @@ def Vector_ReshapeOp :
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In the examples below, valid data elements are represented by an alphabetic
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character, and undefined data elements are represented by '-'.
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- Example
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-
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+ Example:
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+ ```mlir
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vector<1x8xf32> with valid data shape [6], fixed vector sizes [8]
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input: [a, b, c, d, e, f]
@@ -719,8 +718,9 @@ def Vector_ReshapeOp :
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vector layout: [a, b, c, d, e, f, -, -]
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- Example
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-
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+ ```
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+ Example:
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+ ```mlir
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vector<2x8xf32> with valid data shape [10], fixed vector sizes [8]
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input: [a, b, c, d, e, f, g, h, i, j]
@@ -729,9 +729,9 @@ def Vector_ReshapeOp :
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vector layout: [[a, b, c, d, e, f, g, h],
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[i, j, -, -, -, -, -, -]]
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-
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- Example
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-
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+ ```
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+ Example:
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+ ```mlir
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vector<2x2x2x3xf32> with valid data shape [3, 5], fixed vector sizes
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[2, 3]
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@@ -750,9 +750,9 @@ def Vector_ReshapeOp :
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[-, -, -]]
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[[n, o, -],
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[-, -, -]]]]
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-
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- Example
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-
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+ ```
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+ Example:
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+ ```mlir
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%1 = vector.reshape %0, [%c3, %c6], [%c2, %c9], [4]
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: vector<3x2x4xf32> to vector<2x3x4xf32>
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@@ -776,6 +776,7 @@ def Vector_ReshapeOp :
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[[j, k, l, m],
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[n, o, p, q],
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[r, -, -, -]]]
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+ ```
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}];
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let extraClassDeclaration = [{
@@ -828,7 +829,7 @@ def Vector_StridedSliceOp :
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`offsets` and ending at `offsets + sizes`.
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Examples:
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- ```
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+ ```mlir
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%1 = vector.strided_slice %0
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{offsets = [0, 2], sizes = [2, 4], strides = [1, 1]}:
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vector<4x8x16xf32> to vector<2x4x16xf32>
@@ -947,13 +948,12 @@ def Vector_TransferReadOp :
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implemented using a warp-shuffle if loop `j` were mapped to `threadIdx.x`.
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Syntax
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- ```
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+ ```mlir
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operation ::= ssa-id `=` `vector.transfer_read` ssa-use-list
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`{` attribute-entry `} :` memref-type `,` vector-type
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```
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Examples:
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-
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```mlir
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// Read the slice `%A[%i0, %i1:%i1+256, %i2:%i2+32]` into vector<32x256xf32>
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// and pad with %f0 to handle the boundary case:
@@ -1028,7 +1028,7 @@ def Vector_TransferWriteOp :
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Syntax:
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- ```
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+ ```mlir
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operation ::= `vector.transfer_write` ssa-use-list `{` attribute-entry `} :
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` vector-type ', ' memref-type '
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```
@@ -1139,7 +1139,7 @@ def Vector_TypeCastOp :
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Syntax:
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- ```
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+ ```mlir
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operation ::= `vector.type_cast` ssa-use : memref-type to memref-type
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```
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@@ -1183,8 +1183,10 @@ def Vector_ConstantMaskOp :
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define a hyper-rectangular region within which elements values are set to 1
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(otherwise element values are set to 0).
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- Example: create a constant vector mask of size 4x3xi1 with elements in range
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- 0 <= row <= 2 and 0 <= col <= 1 are set to 1 (others to 0).
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+ Example:
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+ ```
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+ create a constant vector mask of size 4x3xi1 with elements in range
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+ 0 <= row <= 2 and 0 <= col <= 1 are set to 1 (others to 0).
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%1 = vector.constant_mask [3, 2] : vector<4x3xi1>
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@@ -1196,6 +1198,7 @@ def Vector_ConstantMaskOp :
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rows 1 | 1 1 0
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2 | 1 1 0
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3 | 0 0 0
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+ ```
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}];
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let extraClassDeclaration = [{
@@ -1217,8 +1220,10 @@ def Vector_CreateMaskOp :
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hyper-rectangular region within which elements values are set to 1
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(otherwise element values are set to 0).
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- Example: create a vector mask of size 4x3xi1 where elements in range
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- 0 <= row <= 2 and 0 <= col <= 1 are set to 1 (others to 0).
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+ Example:
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+ ```
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+ create a vector mask of size 4x3xi1 where elements in range
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+ 0 <= row <= 2 and 0 <= col <= 1 are set to 1 (others to 0).
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%1 = vector.create_mask %c3, %c2 : vector<4x3xi1>
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@@ -1230,6 +1235,7 @@ def Vector_CreateMaskOp :
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rows 1 | 1 1 0
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2 | 1 1 0
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3 | 0 0 0
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+ ```
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}];
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let hasCanonicalizer = 1;
@@ -1248,9 +1254,8 @@ def Vector_TupleOp :
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transformation and should be removed before lowering to lower-level
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dialects.
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-
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Examples:
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- ```
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+ ```mlir
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%0 = vector.transfer_read ... : vector<2x2xf32>
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%1 = vector.transfer_read ... : vector<2x1xf32>
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%2 = vector.transfer_read ... : vector<2x2xf32>
@@ -1280,20 +1285,21 @@ def Vector_TransposeOp :
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Takes a n-D vector and returns the transposed n-D vector defined by
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the permutation of ranks in the n-sized integer array attribute.
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In the operation
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-
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- %1 = vector.tranpose %0, [i_1, .., i_n]
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- : vector<d_1 x .. x d_n x f32>
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- to vector<d_trans[0] x .. x d_trans[n-1] x f32>
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-
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+ ```mlir
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+ %1 = vector.tranpose %0, [i_1, .., i_n]
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+ : vector<d_1 x .. x d_n x f32>
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+ to vector<d_trans[0] x .. x d_trans[n-1] x f32>
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+ ```
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the transp array [i_1, .., i_n] must be a permutation of [0, .., n-1].
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Example:
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-
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+ ```mlir
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%1 = vector.tranpose %0, [1, 0] : vector<2x3xf32> to vector<3x2xf32>
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[ [a, b, c], [ [a, d],
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[d, e, f] ] -> [b, e],
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[c, f] ]
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+ ```
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}];
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let extraClassDeclaration = [{
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VectorType getVectorType() {
@@ -1321,7 +1327,7 @@ def Vector_TupleGetOp :
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dialects.
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Examples:
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- ```
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+ ```mlir
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%4 = vector.tuple %0, %1, %2, %3
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: vector<2x2xf32>, vector<2x1xf32>, vector<2x2xf32>, vector<2x1xf32>>
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@@ -1351,7 +1357,7 @@ def Vector_PrintOp :
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format (for testing and debugging). No return value.
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Examples:
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- ```
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+ ```mlir
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%0 = constant 0.0 : f32
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%1 = vector.broadcast %0 : f32 to vector<4xf32>
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vector.print %1 : vector<4xf32>
@@ -1414,7 +1420,7 @@ def Vector_MatmulOp : Vector_Op<"matrix_multiply", [NoSideEffect,
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Example:
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- ```
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+ ```mlir
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%C = vector.matrix_multiply %A, %B
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{ lhs_rows = 4: i32, lhs_columns = 16: i32 , rhs_columns = 3: i32 } :
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(vector<64xf64>, vector<48xf64>) -> vector<12xf64>
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