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[TargetRegisterInfo] Default trackLivenessAfterRegAlloc() to true
Except AMDGPU/R600RegisterInfo (a bunch of MIR tests seem to have problems), every target overrides it with true. PostMachineScheduler requires livein information. Not providing it can cause assertion failures in ScheduleDAGInstrs::addSchedBarrierDeps().
1 parent 84217ad commit 8e8a75a

23 files changed

+5
-78
lines changed

‎llvm/include/llvm/CodeGen/TargetRegisterInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -855,7 +855,7 @@ class TargetRegisterInfo : public MCRegisterInfo {
855855

856856
/// Returns true if the live-ins should be tracked after register allocation.
857857
virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
858-
return false;
858+
return true;
859859
}
860860

861861
/// True if the stack can be realigned for the target.

‎llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -823,9 +823,6 @@ bool FalkorHWPFFix::runOnMachineFunction(MachineFunction &Fn) {
823823
TII = static_cast<const AArch64InstrInfo *>(ST.getInstrInfo());
824824
TRI = ST.getRegisterInfo();
825825

826-
assert(TRI->trackLivenessAfterRegAlloc(Fn) &&
827-
"Register liveness not available!");
828-
829826
MachineLoopInfo &LI = getAnalysis<MachineLoopInfo>();
830827

831828
Modified = false;

‎llvm/lib/Target/AArch64/AArch64RegisterInfo.h

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -118,10 +118,6 @@ class AArch64RegisterInfo final : public AArch64GenRegisterInfo {
118118
unsigned getRegPressureLimit(const TargetRegisterClass *RC,
119119
MachineFunction &MF) const override;
120120

121-
bool trackLivenessAfterRegAlloc(const MachineFunction&) const override {
122-
return true;
123-
}
124-
125121
unsigned getLocalAddressRegister(const MachineFunction &MF) const;
126122
};
127123

‎llvm/lib/Target/AMDGPU/R600RegisterInfo.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,10 @@ struct R600RegisterInfo final : public R600GenRegisterInfo {
4040
const RegClassWeight &
4141
getRegClassWeight(const TargetRegisterClass *RC) const override;
4242

43+
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
44+
return false;
45+
}
46+
4347
// \returns true if \p Reg can be defined in one ALU clause and used in
4448
// another.
4549
bool isPhysRegLiveAcrossClauses(unsigned Reg) const;

‎llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -305,11 +305,6 @@ bool SIRegisterInfo::requiresVirtualBaseRegisters(
305305
return true;
306306
}
307307

308-
bool SIRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
309-
// This helps catch bugs as verifier errors.
310-
return true;
311-
}
312-
313308
int64_t SIRegisterInfo::getMUBUFInstrOffset(const MachineInstr *MI) const {
314309
assert(SIInstrInfo::isMUBUF(*MI));
315310

‎llvm/lib/Target/AMDGPU/SIRegisterInfo.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -77,7 +77,6 @@ class SIRegisterInfo final : public AMDGPURegisterInfo {
7777
bool requiresFrameIndexReplacementScavenging(
7878
const MachineFunction &MF) const override;
7979
bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override;
80-
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
8180

8281
int64_t getMUBUFInstrOffset(const MachineInstr *MI) const;
8382

‎llvm/lib/Target/ARC/ARCRegisterInfo.cpp

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -153,11 +153,6 @@ bool ARCRegisterInfo::requiresRegisterScavenging(
153153
return true;
154154
}
155155

156-
bool ARCRegisterInfo::trackLivenessAfterRegAlloc(
157-
const MachineFunction &MF) const {
158-
return true;
159-
}
160-
161156
bool ARCRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
162157
return true;
163158
}

‎llvm/lib/Target/ARC/ARCRegisterInfo.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -34,8 +34,6 @@ struct ARCRegisterInfo : public ARCGenRegisterInfo {
3434

3535
bool requiresRegisterScavenging(const MachineFunction &MF) const override;
3636

37-
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
38-
3937
bool useFPForScavengingIndex(const MachineFunction &MF) const override;
4038

4139
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,

‎llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -479,11 +479,6 @@ requiresRegisterScavenging(const MachineFunction &MF) const {
479479
return true;
480480
}
481481

482-
bool ARMBaseRegisterInfo::
483-
trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
484-
return true;
485-
}
486-
487482
bool ARMBaseRegisterInfo::
488483
requiresFrameIndexScavenging(const MachineFunction &MF) const {
489484
return true;

‎llvm/lib/Target/ARM/ARMBaseRegisterInfo.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -192,8 +192,6 @@ class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
192192
/// Code Generation virtual methods...
193193
bool requiresRegisterScavenging(const MachineFunction &MF) const override;
194194

195-
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
196-
197195
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
198196

199197
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;

‎llvm/lib/Target/AVR/AVRRegisterInfo.h

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -51,10 +51,6 @@ class AVRRegisterInfo : public AVRGenRegisterInfo {
5151
/// \param Reg A 16-bit register to split.
5252
void splitReg(unsigned Reg, unsigned &LoReg, unsigned &HiReg) const;
5353

54-
bool trackLivenessAfterRegAlloc(const MachineFunction &) const override {
55-
return true;
56-
}
57-
5854
bool shouldCoalesce(MachineInstr *MI,
5955
const TargetRegisterClass *SrcRC,
6056
unsigned SubReg,

‎llvm/lib/Target/Hexagon/HexagonRegisterInfo.h

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -56,10 +56,6 @@ class HexagonRegisterInfo : public HexagonGenRegisterInfo {
5656
/// Returns true if the frame pointer is valid.
5757
bool useFPForScavengingIndex(const MachineFunction &MF) const override;
5858

59-
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
60-
return true;
61-
}
62-
6359
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
6460
unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg,
6561
const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override;

‎llvm/lib/Target/Lanai/LanaiRegisterInfo.cpp

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -66,11 +66,6 @@ bool LanaiRegisterInfo::requiresRegisterScavenging(
6666
return true;
6767
}
6868

69-
bool LanaiRegisterInfo::trackLivenessAfterRegAlloc(
70-
const MachineFunction & /*MF*/) const {
71-
return true;
72-
}
73-
7469
static bool isALUArithLoOpcode(unsigned Opcode) {
7570
switch (Opcode) {
7671
case Lanai::ADD_I_LO:

‎llvm/lib/Target/Lanai/LanaiRegisterInfo.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -34,8 +34,6 @@ struct LanaiRegisterInfo : public LanaiGenRegisterInfo {
3434

3535
bool requiresRegisterScavenging(const MachineFunction &MF) const override;
3636

37-
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
38-
3937
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
4038
unsigned FIOperandNum,
4139
RegScavenger *RS = nullptr) const override;

‎llvm/lib/Target/Mips/MipsRegisterInfo.cpp

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -245,11 +245,6 @@ MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
245245
return true;
246246
}
247247

248-
bool
249-
MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
250-
return true;
251-
}
252-
253248
// FrameIndex represent objects inside a abstract stack.
254249
// We must replace FrameIndex with an stack/frame pointer
255250
// direct reference.

‎llvm/lib/Target/Mips/MipsRegisterInfo.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -58,8 +58,6 @@ class MipsRegisterInfo : public MipsGenRegisterInfo {
5858

5959
bool requiresRegisterScavenging(const MachineFunction &MF) const override;
6060

61-
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
62-
6361
/// Stack Frame Processing Methods
6462
void eliminateFrameIndex(MachineBasicBlock::iterator II,
6563
int SPAdj, unsigned FIOperandNum,

‎llvm/lib/Target/PowerPC/PPCRegisterInfo.h

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -101,10 +101,6 @@ class PPCRegisterInfo : public PPCGenRegisterInfo {
101101

102102
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
103103

104-
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
105-
return true;
106-
}
107-
108104
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override {
109105
return true;
110106
}

‎llvm/lib/Target/RISCV/RISCVRegisterInfo.h

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -51,10 +51,6 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
5151
return true;
5252
}
5353

54-
bool trackLivenessAfterRegAlloc(const MachineFunction &) const override {
55-
return true;
56-
}
57-
5854
const TargetRegisterClass *
5955
getPointerRegClass(const MachineFunction &MF,
6056
unsigned Kind = 0) const override {

‎llvm/lib/Target/SystemZ/SystemZRegisterInfo.h

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -72,9 +72,6 @@ struct SystemZRegisterInfo : public SystemZGenRegisterInfo {
7272
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
7373
return true;
7474
}
75-
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
76-
return true;
77-
}
7875
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
7976
const uint32_t *getCallPreservedMask(const MachineFunction &MF,
8077
CallingConv::ID CC) const override;

‎llvm/lib/Target/X86/X86RegisterInfo.cpp

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -72,12 +72,6 @@ X86RegisterInfo::X86RegisterInfo(const Triple &TT)
7272
}
7373
}
7474

75-
bool
76-
X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
77-
// ExecutionDomainFix, BreakFalseDeps and PostRAScheduler require liveness.
78-
return true;
79-
}
80-
8175
int
8276
X86RegisterInfo::getSEHRegNum(unsigned i) const {
8377
return getEncodingValue(i);

‎llvm/lib/Target/X86/X86RegisterInfo.h

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -54,10 +54,6 @@ class X86RegisterInfo final : public X86GenRegisterInfo {
5454
// FIXME: This should be tablegen'd like getDwarfRegNum is
5555
int getSEHRegNum(unsigned i) const;
5656

57-
/// Code Generation virtual methods...
58-
///
59-
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
60-
6157
/// getMatchingSuperRegClass - Return a subclass of the specified register
6258
/// class A so that each register in it has a sub-register of the
6359
/// specified sub-register index which is in the specified register class B.

‎llvm/lib/Target/XCore/XCoreRegisterInfo.cpp

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -245,11 +245,6 @@ XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
245245
return true;
246246
}
247247

248-
bool
249-
XCoreRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
250-
return true;
251-
}
252-
253248
bool
254249
XCoreRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
255250
return false;

‎llvm/lib/Target/XCore/XCoreRegisterInfo.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -34,8 +34,6 @@ struct XCoreRegisterInfo : public XCoreGenRegisterInfo {
3434

3535
bool requiresRegisterScavenging(const MachineFunction &MF) const override;
3636

37-
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
38-
3937
bool useFPForScavengingIndex(const MachineFunction &MF) const override;
4038

4139
void eliminateFrameIndex(MachineBasicBlock::iterator II,

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