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GlobalISel: Merge FewerElements for G_BUILD_VECTOR/G_CONCAT_VECTORS
This switches from using G_EXTRACT in odd cases to widen with undef and unmerge.
1 parent 42b993d commit 901e331

40 files changed

+339
-303
lines changed

‎llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -287,15 +287,12 @@ class LegalizerHelper {
287287
LegalizeResult fewerElementsVectorUnmergeValues(MachineInstr &MI,
288288
unsigned TypeIdx,
289289
LLT NarrowTy);
290-
LegalizeResult fewerElementsVectorBuildVector(MachineInstr &MI,
291-
unsigned TypeIdx,
292-
LLT NarrowTy);
293-
LegalizeResult fewerElementsVectorConcatVectors(MachineInstr &MI,
294-
unsigned TypeIdx,
295-
LLT NarrowTy);
290+
LegalizeResult fewerElementsVectorMerge(MachineInstr &MI, unsigned TypeIdx,
291+
LLT NarrowTy);
296292
LegalizeResult fewerElementsVectorExtractInsertVectorElt(MachineInstr &MI,
297293
unsigned TypeIdx,
298294
LLT NarrowTy);
295+
299296
LegalizeResult
300297
reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
301298

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 22 additions & 67 deletions
Original file line numberDiff line numberDiff line change
@@ -3555,72 +3555,24 @@ LegalizerHelper::fewerElementsVectorUnmergeValues(MachineInstr &MI,
35553555
return Legalized;
35563556
}
35573557

3558+
// Handle FewerElementsVector a G_BUILD_VECTOR or G_CONCAT_VECTORS that produces
3559+
// a vector
3560+
//
3561+
// Create a G_BUILD_VECTOR or G_CONCAT_VECTORS of NarrowTy pieces, padding with
3562+
// undef as necessary.
3563+
//
3564+
// %3:_(<3 x s16>) = G_BUILD_VECTOR %0, %1, %2
3565+
// -> <2 x s16>
3566+
//
3567+
// %4:_(s16) = G_IMPLICIT_DEF
3568+
// %5:_(<2 x s16>) = G_BUILD_VECTOR %0, %1
3569+
// %6:_(<2 x s16>) = G_BUILD_VECTOR %2, %4
3570+
// %7:_(<2 x s16>) = G_IMPLICIT_DEF
3571+
// %8:_(<6 x s16>) = G_CONCAT_VECTORS %5, %6, %7
3572+
// %3:_(<3 x s16>), %8:_(<3 x s16>) = G_UNMERGE_VALUES %8
35583573
LegalizerHelper::LegalizeResult
3559-
LegalizerHelper::fewerElementsVectorBuildVector(MachineInstr &MI,
3560-
unsigned TypeIdx,
3561-
LLT NarrowTy) {
3562-
assert(TypeIdx == 0 && "not a vector type index");
3563-
Register DstReg = MI.getOperand(0).getReg();
3564-
LLT DstTy = MRI.getType(DstReg);
3565-
LLT SrcTy = DstTy.getElementType();
3566-
3567-
int DstNumElts = DstTy.getNumElements();
3568-
int NarrowNumElts = NarrowTy.getNumElements();
3569-
int NumConcat = (DstNumElts + NarrowNumElts - 1) / NarrowNumElts;
3570-
LLT WidenedDstTy = LLT::vector(NarrowNumElts * NumConcat, SrcTy);
3571-
3572-
SmallVector<Register, 8> ConcatOps;
3573-
SmallVector<Register, 8> SubBuildVector;
3574-
3575-
Register UndefReg;
3576-
if (WidenedDstTy != DstTy)
3577-
UndefReg = MIRBuilder.buildUndef(SrcTy).getReg(0);
3578-
3579-
// Create a G_CONCAT_VECTORS of NarrowTy pieces, padding with undef as
3580-
// necessary.
3581-
//
3582-
// %3:_(<3 x s16>) = G_BUILD_VECTOR %0, %1, %2
3583-
// -> <2 x s16>
3584-
//
3585-
// %4:_(s16) = G_IMPLICIT_DEF
3586-
// %5:_(<2 x s16>) = G_BUILD_VECTOR %0, %1
3587-
// %6:_(<2 x s16>) = G_BUILD_VECTOR %2, %4
3588-
// %7:_(<4 x s16>) = G_CONCAT_VECTORS %5, %6
3589-
// %3:_(<3 x s16>) = G_EXTRACT %7, 0
3590-
for (int I = 0; I != NumConcat; ++I) {
3591-
for (int J = 0; J != NarrowNumElts; ++J) {
3592-
int SrcIdx = NarrowNumElts * I + J;
3593-
3594-
if (SrcIdx < DstNumElts) {
3595-
Register SrcReg = MI.getOperand(SrcIdx + 1).getReg();
3596-
SubBuildVector.push_back(SrcReg);
3597-
} else
3598-
SubBuildVector.push_back(UndefReg);
3599-
}
3600-
3601-
auto BuildVec = MIRBuilder.buildBuildVector(NarrowTy, SubBuildVector);
3602-
ConcatOps.push_back(BuildVec.getReg(0));
3603-
SubBuildVector.clear();
3604-
}
3605-
3606-
if (DstTy == WidenedDstTy)
3607-
MIRBuilder.buildConcatVectors(DstReg, ConcatOps);
3608-
else {
3609-
auto Concat = MIRBuilder.buildConcatVectors(WidenedDstTy, ConcatOps);
3610-
MIRBuilder.buildExtract(DstReg, Concat, 0);
3611-
}
3612-
3613-
MI.eraseFromParent();
3614-
return Legalized;
3615-
}
3616-
3617-
LegalizerHelper::LegalizeResult
3618-
LegalizerHelper::fewerElementsVectorConcatVectors(MachineInstr &MI,
3619-
unsigned TypeIdx,
3620-
LLT NarrowTy) {
3621-
if (TypeIdx != 1)
3622-
return UnableToLegalize;
3623-
3574+
LegalizerHelper::fewerElementsVectorMerge(MachineInstr &MI, unsigned TypeIdx,
3575+
LLT NarrowTy) {
36243576
Register DstReg = MI.getOperand(0).getReg();
36253577
LLT DstTy = MRI.getType(DstReg);
36263578
LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
@@ -4045,9 +3997,12 @@ LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
40453997
case G_UNMERGE_VALUES:
40463998
return fewerElementsVectorUnmergeValues(MI, TypeIdx, NarrowTy);
40473999
case G_BUILD_VECTOR:
4048-
return fewerElementsVectorBuildVector(MI, TypeIdx, NarrowTy);
4000+
assert(TypeIdx == 0 && "not a vector type index");
4001+
return fewerElementsVectorMerge(MI, TypeIdx, NarrowTy);
40494002
case G_CONCAT_VECTORS:
4050-
return fewerElementsVectorConcatVectors(MI, TypeIdx, NarrowTy);
4003+
if (TypeIdx != 1) // TODO: This probably does work as expected already.
4004+
return UnableToLegalize;
4005+
return fewerElementsVectorMerge(MI, TypeIdx, NarrowTy);
40514006
case G_EXTRACT_VECTOR_ELT:
40524007
case G_INSERT_VECTOR_ELT:
40534008
return fewerElementsVectorExtractInsertVectorElt(MI, TypeIdx, NarrowTy);

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -800,8 +800,9 @@ body: |
800800
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
801801
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[SHL1]]
802802
; SI: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
803-
; SI: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
804-
; SI: [[EXTRACT2:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
803+
; SI: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
804+
; SI: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[DEF1]](<2 x s16>)
805+
; SI: [[EXTRACT2:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0
805806
; SI: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT2]](<3 x s16>), 0
806807
; SI: $vgpr0_vgpr1 = COPY [[INSERT2]](<4 x s16>)
807808
; VI-LABEL: name: test_ashr_v3s16_v3s16
@@ -842,8 +843,9 @@ body: |
842843
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C]](s32)
843844
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
844845
; VI: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
845-
; VI: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
846-
; VI: [[EXTRACT2:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
846+
; VI: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
847+
; VI: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[DEF1]](<2 x s16>)
848+
; VI: [[EXTRACT2:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0
847849
; VI: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT2]](<3 x s16>), 0
848850
; VI: $vgpr0_vgpr1 = COPY [[INSERT2]](<4 x s16>)
849851
; GFX9-LABEL: name: test_ashr_v3s16_v3s16

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -398,10 +398,11 @@ body: |
398398
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
399399
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
400400
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
401-
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
402-
; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
403-
; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
404-
; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0
401+
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
402+
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[DEF]](<2 x s16>)
403+
; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0
404+
; CHECK: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
405+
; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[EXTRACT]](<3 x s16>), 0
405406
; CHECK: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>)
406407
; CHECK: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
407408
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
@@ -1553,8 +1554,9 @@ body: |
15531554
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[C2]](s32)
15541555
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
15551556
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
1556-
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
1557-
; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
1557+
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
1558+
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[DEF]](<2 x s16>)
1559+
; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0
15581560
; CHECK: S_ENDPGM 0, implicit [[EXTRACT]](<3 x s16>)
15591561
%0:_(<6 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
15601562
%1:_(<6 x s8>) = G_TRUNC %0

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir

Lines changed: 18 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -62,8 +62,9 @@ body: |
6262
; GFX78: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C1]](s32)
6363
; GFX78: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
6464
; GFX78: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
65-
; GFX78: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
66-
; GFX78: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
65+
; GFX78: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
66+
; GFX78: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[DEF]](<2 x s16>)
67+
; GFX78: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0
6768
; GFX78: S_NOP 0, implicit [[EXTRACT]](<3 x s16>)
6869
; GFX9-LABEL: name: build_vector_v3s16
6970
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
@@ -75,8 +76,9 @@ body: |
7576
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
7677
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
7778
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[DEF]](s32)
78-
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
79-
; GFX9: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
79+
; GFX9: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
80+
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[DEF1]](<2 x s16>)
81+
; GFX9: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0
8082
; GFX9: S_NOP 0, implicit [[EXTRACT]](<3 x s16>)
8183
%0:_(s32) = COPY $vgpr0
8284
%1:_(s32) = COPY $vgpr1
@@ -176,8 +178,9 @@ body: |
176178
; GFX78: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C1]](s32)
177179
; GFX78: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
178180
; GFX78: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
179-
; GFX78: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>)
180-
; GFX78: [[EXTRACT:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0
181+
; GFX78: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
182+
; GFX78: [[CONCAT_VECTORS:%[0-9]+]]:_(<10 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>)
183+
; GFX78: [[EXTRACT:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<10 x s16>), 0
181184
; GFX78: S_NOP 0, implicit [[EXTRACT]](<5 x s16>)
182185
; GFX9-LABEL: name: build_vector_v5s16
183186
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
@@ -194,8 +197,9 @@ body: |
194197
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
195198
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
196199
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[DEF]](s32)
197-
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
198-
; GFX9: [[EXTRACT:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0
200+
; GFX9: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
201+
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<10 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[DEF1]](<2 x s16>), [[DEF1]](<2 x s16>)
202+
; GFX9: [[EXTRACT:%[0-9]+]]:_(<5 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<10 x s16>), 0
199203
; GFX9: S_NOP 0, implicit [[EXTRACT]](<5 x s16>)
200204
%0:_(s32) = COPY $vgpr0
201205
%1:_(s32) = COPY $vgpr1
@@ -254,8 +258,9 @@ body: |
254258
; GFX78: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C1]](s32)
255259
; GFX78: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
256260
; GFX78: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
257-
; GFX78: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>)
258-
; GFX78: [[EXTRACT:%[0-9]+]]:_(<7 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<8 x s16>), 0
261+
; GFX78: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
262+
; GFX78: [[CONCAT_VECTORS:%[0-9]+]]:_(<14 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>)
263+
; GFX78: [[EXTRACT:%[0-9]+]]:_(<7 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<14 x s16>), 0
259264
; GFX78: S_NOP 0, implicit [[EXTRACT]](<7 x s16>)
260265
; GFX9-LABEL: name: build_vector_v7s16
261266
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
@@ -277,8 +282,9 @@ body: |
277282
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
278283
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
279284
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
280-
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>)
281-
; GFX9: [[EXTRACT:%[0-9]+]]:_(<7 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<8 x s16>), 0
285+
; GFX9: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
286+
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<14 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>), [[DEF1]](<2 x s16>), [[DEF1]](<2 x s16>), [[DEF1]](<2 x s16>)
287+
; GFX9: [[EXTRACT:%[0-9]+]]:_(<7 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<14 x s16>), 0
282288
; GFX9: S_NOP 0, implicit [[EXTRACT]](<7 x s16>)
283289
%0:_(s32) = COPY $vgpr0
284290
%1:_(s32) = COPY $vgpr1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -541,10 +541,11 @@ body: |
541541
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C]](s32)
542542
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
543543
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
544-
; CHECK: [[CONCAT_VECTORS1:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
545-
; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS1]](<4 x s16>), 0
546-
; CHECK: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
547-
; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF2]], [[EXTRACT]](<3 x s16>), 0
544+
; CHECK: [[DEF2:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
545+
; CHECK: [[CONCAT_VECTORS1:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[DEF2]](<2 x s16>)
546+
; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS1]](<6 x s16>), 0
547+
; CHECK: [[DEF3:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
548+
; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF3]], [[EXTRACT]](<3 x s16>), 0
548549
; CHECK: [[EXTRACT1:%[0-9]+]]:_(s16) = G_EXTRACT [[INSERT]](<4 x s16>), 32
549550
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT1]](s16)
550551
; CHECK: $vgpr0 = COPY [[ANYEXT3]](s32)

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -377,8 +377,9 @@ body: |
377377
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C]](s32)
378378
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
379379
; SI: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
380-
; SI: [[CONCAT_VECTORS2:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
381-
; SI: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS2]](<4 x s16>), 0
380+
; SI: [[DEF3:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
381+
; SI: [[CONCAT_VECTORS2:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[DEF3]](<2 x s16>)
382+
; SI: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS2]](<6 x s16>), 0
382383
; SI: S_NOP 0, implicit [[EXTRACT]](<3 x s16>)
383384
; VI-LABEL: name: test_fadd_v3s16
384385
; VI: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
@@ -420,8 +421,9 @@ body: |
420421
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C]](s32)
421422
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
422423
; VI: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
423-
; VI: [[CONCAT_VECTORS2:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
424-
; VI: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS2]](<4 x s16>), 0
424+
; VI: [[DEF3:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
425+
; VI: [[CONCAT_VECTORS2:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[DEF3]](<2 x s16>)
426+
; VI: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS2]](<6 x s16>), 0
425427
; VI: S_NOP 0, implicit [[EXTRACT]](<3 x s16>)
426428
; GFX9-LABEL: name: test_fadd_v3s16
427429
; GFX9: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -254,8 +254,9 @@ body: |
254254
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C]](s32)
255255
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
256256
; SI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
257-
; SI: [[CONCAT_VECTORS1:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>)
258-
; SI: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS1]](<4 x s16>), 0
257+
; SI: [[DEF2:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
258+
; SI: [[CONCAT_VECTORS1:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[DEF2]](<2 x s16>)
259+
; SI: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS1]](<6 x s16>), 0
259260
; SI: S_NOP 0, implicit [[EXTRACT]](<3 x s16>)
260261
; VI-LABEL: name: test_fcanonicalize_v3s16
261262
; VI: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
@@ -285,8 +286,9 @@ body: |
285286
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C]](s32)
286287
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
287288
; VI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
288-
; VI: [[CONCAT_VECTORS1:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>)
289-
; VI: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS1]](<4 x s16>), 0
289+
; VI: [[DEF2:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
290+
; VI: [[CONCAT_VECTORS1:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[DEF2]](<2 x s16>)
291+
; VI: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS1]](<6 x s16>), 0
290292
; VI: S_NOP 0, implicit [[EXTRACT]](<3 x s16>)
291293
; GFX9-LABEL: name: test_fcanonicalize_v3s16
292294
; GFX9: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF

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