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HsiangkaiHsiangkai
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[NFC] Use generic name for scalable vector stack ID.
Differential Revision: https://reviews.llvm.org/D94471
1 parent bba3a82 commit 914e2f5

18 files changed

+86
-86
lines changed

‎llvm/include/llvm/CodeGen/MIRYamlMapping.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -347,7 +347,7 @@ struct ScalarEnumerationTraits<TargetStackID::Value> {
347347
static void enumeration(yaml::IO &IO, TargetStackID::Value &ID) {
348348
IO.enumCase(ID, "default", TargetStackID::Default);
349349
IO.enumCase(ID, "sgpr-spill", TargetStackID::SGPRSpill);
350-
IO.enumCase(ID, "sve-vec", TargetStackID::SVEVector);
350+
IO.enumCase(ID, "scalable-vector", TargetStackID::ScalableVector);
351351
IO.enumCase(ID, "noalloc", TargetStackID::NoAlloc);
352352
}
353353
};

‎llvm/include/llvm/CodeGen/TargetFrameLowering.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ namespace TargetStackID {
2727
enum Value {
2828
Default = 0,
2929
SGPRSpill = 1,
30-
SVEVector = 2,
30+
ScalableVector = 2,
3131
NoAlloc = 255
3232
};
3333
}

‎llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -249,7 +249,7 @@ static unsigned estimateRSStackSizeLimit(MachineFunction &MF) {
249249

250250
TargetStackID::Value
251251
AArch64FrameLowering::getStackIDForScalableVectors() const {
252-
return TargetStackID::SVEVector;
252+
return TargetStackID::ScalableVector;
253253
}
254254

255255
/// Returns the size of the fixed object area (allocated next to sp on entry)
@@ -496,7 +496,7 @@ void AArch64FrameLowering::emitCalleeSavedFrameMoves(
496496
continue;
497497

498498
StackOffset Offset;
499-
if (MFI.getStackID(Info.getFrameIdx()) == TargetStackID::SVEVector) {
499+
if (MFI.getStackID(Info.getFrameIdx()) == TargetStackID::ScalableVector) {
500500
AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
501501
Offset =
502502
StackOffset::getScalable(MFI.getObjectOffset(Info.getFrameIdx())) -
@@ -1856,7 +1856,7 @@ StackOffset AArch64FrameLowering::resolveFrameIndexReference(
18561856
const auto &MFI = MF.getFrameInfo();
18571857
int64_t ObjectOffset = MFI.getObjectOffset(FI);
18581858
bool isFixed = MFI.isFixedObjectIndex(FI);
1859-
bool isSVE = MFI.getStackID(FI) == TargetStackID::SVEVector;
1859+
bool isSVE = MFI.getStackID(FI) == TargetStackID::ScalableVector;
18601860
return resolveFrameOffsetReference(MF, ObjectOffset, isFixed, isSVE, FrameReg,
18611861
PreferFP, ForSimm);
18621862
}
@@ -2412,7 +2412,7 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
24122412
// Update the StackIDs of the SVE stack slots.
24132413
MachineFrameInfo &MFI = MF.getFrameInfo();
24142414
if (RPI.Type == RegPairInfo::ZPR || RPI.Type == RegPairInfo::PPR)
2415-
MFI.setStackID(RPI.FrameIdx, TargetStackID::SVEVector);
2415+
MFI.setStackID(RPI.FrameIdx, TargetStackID::ScalableVector);
24162416

24172417
}
24182418
return true;
@@ -2761,7 +2761,7 @@ static int64_t determineSVEStackObjectOffsets(MachineFrameInfo &MFI,
27612761
#ifndef NDEBUG
27622762
// First process all fixed stack objects.
27632763
for (int I = MFI.getObjectIndexBegin(); I != 0; ++I)
2764-
assert(MFI.getStackID(I) != TargetStackID::SVEVector &&
2764+
assert(MFI.getStackID(I) != TargetStackID::ScalableVector &&
27652765
"SVE vectors should never be passed on the stack by value, only by "
27662766
"reference.");
27672767
#endif
@@ -2791,7 +2791,7 @@ static int64_t determineSVEStackObjectOffsets(MachineFrameInfo &MFI,
27912791
SmallVector<int, 8> ObjectsToAllocate;
27922792
for (int I = 0, E = MFI.getObjectIndexEnd(); I != E; ++I) {
27932793
unsigned StackID = MFI.getStackID(I);
2794-
if (StackID != TargetStackID::SVEVector)
2794+
if (StackID != TargetStackID::ScalableVector)
27952795
continue;
27962796
if (MaxCSFrameIndex >= I && I >= MinCSFrameIndex)
27972797
continue;

‎llvm/lib/Target/AArch64/AArch64FrameLowering.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -107,7 +107,7 @@ class AArch64FrameLowering : public TargetFrameLowering {
107107
default:
108108
return false;
109109
case TargetStackID::Default:
110-
case TargetStackID::SVEVector:
110+
case TargetStackID::ScalableVector:
111111
case TargetStackID::NoAlloc:
112112
return true;
113113
}
@@ -116,7 +116,7 @@ class AArch64FrameLowering : public TargetFrameLowering {
116116
bool isStackIdSafeForLocalArea(unsigned StackId) const override {
117117
// We don't support putting SVE objects into the pre-allocated local
118118
// frame block at the moment.
119-
return StackId != TargetStackID::SVEVector;
119+
return StackId != TargetStackID::ScalableVector;
120120
}
121121

122122
void

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5400,7 +5400,7 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
54005400
Type *Ty = EVT(VA.getValVT()).getTypeForEVT(*DAG.getContext());
54015401
Align Alignment = DAG.getDataLayout().getPrefTypeAlign(Ty);
54025402
int FI = MFI.CreateStackObject(StoreSize, Alignment, false);
5403-
MFI.setStackID(FI, TargetStackID::SVEVector);
5403+
MFI.setStackID(FI, TargetStackID::ScalableVector);
54045404

54055405
MachinePointerInfo MPI =
54065406
MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -3291,7 +3291,7 @@ void AArch64InstrInfo::storeRegToStackSlot(
32913291
else if (AArch64::PPRRegClass.hasSubClassEq(RC)) {
32923292
assert(Subtarget.hasSVE() && "Unexpected register store without SVE");
32933293
Opc = AArch64::STR_PXI;
3294-
StackID = TargetStackID::SVEVector;
3294+
StackID = TargetStackID::ScalableVector;
32953295
}
32963296
break;
32973297
case 4:
@@ -3335,7 +3335,7 @@ void AArch64InstrInfo::storeRegToStackSlot(
33353335
} else if (AArch64::ZPRRegClass.hasSubClassEq(RC)) {
33363336
assert(Subtarget.hasSVE() && "Unexpected register store without SVE");
33373337
Opc = AArch64::STR_ZXI;
3338-
StackID = TargetStackID::SVEVector;
3338+
StackID = TargetStackID::ScalableVector;
33393339
}
33403340
break;
33413341
case 24:
@@ -3357,7 +3357,7 @@ void AArch64InstrInfo::storeRegToStackSlot(
33573357
} else if (AArch64::ZPR2RegClass.hasSubClassEq(RC)) {
33583358
assert(Subtarget.hasSVE() && "Unexpected register store without SVE");
33593359
Opc = AArch64::STR_ZZXI;
3360-
StackID = TargetStackID::SVEVector;
3360+
StackID = TargetStackID::ScalableVector;
33613361
}
33623362
break;
33633363
case 48:
@@ -3368,7 +3368,7 @@ void AArch64InstrInfo::storeRegToStackSlot(
33683368
} else if (AArch64::ZPR3RegClass.hasSubClassEq(RC)) {
33693369
assert(Subtarget.hasSVE() && "Unexpected register store without SVE");
33703370
Opc = AArch64::STR_ZZZXI;
3371-
StackID = TargetStackID::SVEVector;
3371+
StackID = TargetStackID::ScalableVector;
33723372
}
33733373
break;
33743374
case 64:
@@ -3379,7 +3379,7 @@ void AArch64InstrInfo::storeRegToStackSlot(
33793379
} else if (AArch64::ZPR4RegClass.hasSubClassEq(RC)) {
33803380
assert(Subtarget.hasSVE() && "Unexpected register store without SVE");
33813381
Opc = AArch64::STR_ZZZZXI;
3382-
StackID = TargetStackID::SVEVector;
3382+
StackID = TargetStackID::ScalableVector;
33833383
}
33843384
break;
33853385
}
@@ -3445,7 +3445,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(
34453445
else if (AArch64::PPRRegClass.hasSubClassEq(RC)) {
34463446
assert(Subtarget.hasSVE() && "Unexpected register load without SVE");
34473447
Opc = AArch64::LDR_PXI;
3448-
StackID = TargetStackID::SVEVector;
3448+
StackID = TargetStackID::ScalableVector;
34493449
}
34503450
break;
34513451
case 4:
@@ -3489,7 +3489,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(
34893489
} else if (AArch64::ZPRRegClass.hasSubClassEq(RC)) {
34903490
assert(Subtarget.hasSVE() && "Unexpected register load without SVE");
34913491
Opc = AArch64::LDR_ZXI;
3492-
StackID = TargetStackID::SVEVector;
3492+
StackID = TargetStackID::ScalableVector;
34933493
}
34943494
break;
34953495
case 24:
@@ -3511,7 +3511,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(
35113511
} else if (AArch64::ZPR2RegClass.hasSubClassEq(RC)) {
35123512
assert(Subtarget.hasSVE() && "Unexpected register load without SVE");
35133513
Opc = AArch64::LDR_ZZXI;
3514-
StackID = TargetStackID::SVEVector;
3514+
StackID = TargetStackID::ScalableVector;
35153515
}
35163516
break;
35173517
case 48:
@@ -3522,7 +3522,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(
35223522
} else if (AArch64::ZPR3RegClass.hasSubClassEq(RC)) {
35233523
assert(Subtarget.hasSVE() && "Unexpected register load without SVE");
35243524
Opc = AArch64::LDR_ZZZXI;
3525-
StackID = TargetStackID::SVEVector;
3525+
StackID = TargetStackID::ScalableVector;
35263526
}
35273527
break;
35283528
case 64:
@@ -3533,7 +3533,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(
35333533
} else if (AArch64::ZPR4RegClass.hasSubClassEq(RC)) {
35343534
assert(Subtarget.hasSVE() && "Unexpected register load without SVE");
35353535
Opc = AArch64::LDR_ZZZZXI;
3536-
StackID = TargetStackID::SVEVector;
3536+
StackID = TargetStackID::ScalableVector;
35373537
}
35383538
break;
35393539
}

‎llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -783,7 +783,7 @@ bool SIFrameLowering::isSupportedStackID(TargetStackID::Value ID) const {
783783
case TargetStackID::NoAlloc:
784784
case TargetStackID::SGPRSpill:
785785
return true;
786-
case TargetStackID::SVEVector:
786+
case TargetStackID::ScalableVector:
787787
return false;
788788
}
789789
llvm_unreachable("Invalid TargetStackID::Value");

‎llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -158,33 +158,33 @@ frameInfo:
158158
maxCallFrameSize: 0
159159
localFrameSize: 8
160160
stack:
161-
- { id: 0, name: z0.addr, size: 16, alignment: 16, stack-id: sve-vec,
161+
- { id: 0, name: z0.addr, size: 16, alignment: 16, stack-id: scalable-vector,
162162
debug-info-variable: '!29', debug-info-expression: '!DIExpression()',
163163
debug-info-location: '!30' }
164-
- { id: 1, name: z1.addr, size: 16, alignment: 16, stack-id: sve-vec,
164+
- { id: 1, name: z1.addr, size: 16, alignment: 16, stack-id: scalable-vector,
165165
debug-info-variable: '!31', debug-info-expression: '!DIExpression()',
166166
debug-info-location: '!32' }
167-
- { id: 2, name: p0.addr, size: 2, alignment: 2, stack-id: sve-vec,
167+
- { id: 2, name: p0.addr, size: 2, alignment: 2, stack-id: scalable-vector,
168168
debug-info-variable: '!33', debug-info-expression: '!DIExpression()',
169169
debug-info-location: '!34' }
170-
- { id: 3, name: p1.addr, size: 2, alignment: 2, stack-id: sve-vec,
170+
- { id: 3, name: p1.addr, size: 2, alignment: 2, stack-id: scalable-vector,
171171
debug-info-variable: '!35', debug-info-expression: '!DIExpression()',
172172
debug-info-location: '!36' }
173173
- { id: 4, name: w0.addr, size: 4, alignment: 4, local-offset: -4, debug-info-variable: '!37',
174174
debug-info-expression: '!DIExpression()', debug-info-location: '!38' }
175175
- { id: 5, name: local_gpr0, size: 4, alignment: 4, local-offset: -8,
176176
debug-info-variable: '!39', debug-info-expression: '!DIExpression()',
177177
debug-info-location: '!40' }
178-
- { id: 6, name: localv0, size: 16, alignment: 16, stack-id: sve-vec,
178+
- { id: 6, name: localv0, size: 16, alignment: 16, stack-id: scalable-vector,
179179
debug-info-variable: '!42', debug-info-expression: '!DIExpression()',
180180
debug-info-location: '!43' }
181-
- { id: 7, name: localv1, size: 16, alignment: 16, stack-id: sve-vec,
181+
- { id: 7, name: localv1, size: 16, alignment: 16, stack-id: scalable-vector,
182182
debug-info-variable: '!45', debug-info-expression: '!DIExpression()',
183183
debug-info-location: '!46' }
184-
- { id: 8, name: localp0, size: 2, alignment: 2, stack-id: sve-vec,
184+
- { id: 8, name: localp0, size: 2, alignment: 2, stack-id: scalable-vector,
185185
debug-info-variable: '!48', debug-info-expression: '!DIExpression()',
186186
debug-info-location: '!49' }
187-
- { id: 9, name: localp1, size: 2, alignment: 2, stack-id: sve-vec,
187+
- { id: 9, name: localp1, size: 2, alignment: 2, stack-id: scalable-vector,
188188
debug-info-variable: '!51', debug-info-expression: '!DIExpression()',
189189
debug-info-location: '!52' }
190190
machineFunctionInfo: {}

‎llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -94,10 +94,10 @@ frameInfo:
9494
stack:
9595
- { id: 0, size: 8, alignment: 8 }
9696
- { id: 1, size: 8, alignment: 8 }
97-
- { id: 2, size: 16, alignment: 16, stack-id: sve-vec }
98-
- { id: 3, size: 16, alignment: 16, stack-id: sve-vec }
99-
- { id: 4, size: 2, alignment: 2, stack-id: sve-vec }
100-
- { id: 5, size: 2, alignment: 2, stack-id: sve-vec }
97+
- { id: 2, size: 16, alignment: 16, stack-id: scalable-vector }
98+
- { id: 3, size: 16, alignment: 16, stack-id: scalable-vector }
99+
- { id: 4, size: 2, alignment: 2, stack-id: scalable-vector }
100+
- { id: 5, size: 2, alignment: 2, stack-id: scalable-vector }
101101
machineFunctionInfo: {}
102102
body: |
103103
bb.0.entry:

‎llvm/test/CodeGen/AArch64/framelayout-sve-basepointer.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ frameInfo:
1414
stack:
1515
- { id: 0, type: variable-sized, alignment: 1 }
1616
- { id: 1, name: '', size: 16, alignment: 8 }
17-
- { id: 2, stack-id: sve-vec, size: 16, alignment: 16 }
17+
- { id: 2, stack-id: scalable-vector, size: 16, alignment: 16 }
1818
body: |
1919
bb.0:
2020
liveins: $x0

‎llvm/test/CodeGen/AArch64/framelayout-sve-calleesaves-fix.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@
2424
...
2525
name: fix_restorepoint_p4
2626
stack:
27-
- { id: 0, stack-id: sve-vec, size: 16, alignment: 16 }
27+
- { id: 0, stack-id: scalable-vector, size: 16, alignment: 16 }
2828
body: |
2929
bb.0.entry:
3030
$z8 = IMPLICIT_DEF

‎llvm/test/CodeGen/AArch64/framelayout-sve-scavengingslot.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ frameInfo:
1616
isFrameAddressTaken: true
1717
stack:
1818
- { id: 0, name: '', size: 32761, alignment: 8 }
19-
- { id: 1, stack-id: sve-vec, size: 16, alignment: 16 }
19+
- { id: 1, stack-id: scalable-vector, size: 16, alignment: 16 }
2020
body: |
2121
bb.0:
2222
liveins: $x0, $x8

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