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[X86][NFC] Rename target feature hasCMov->hasCMOV
This is a follow-up patch for D121975.
1 parent 31906a6 commit 920c2e5

10 files changed

+31
-31
lines changed

llvm/lib/Target/X86/X86FastISel.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2036,7 +2036,7 @@ bool X86FastISel::X86SelectDivRem(const Instruction *I) {
20362036
/// the select.
20372037
bool X86FastISel::X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I) {
20382038
// Check if the subtarget supports these instructions.
2039-
if (!Subtarget->hasCMov())
2039+
if (!Subtarget->hasCMOV())
20402040
return false;
20412041

20422042
// FIXME: Add support for i8.

llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5514,7 +5514,7 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
55145514
MVT CmpVT = N0.getSimpleValueType();
55155515

55165516
// Floating point needs special handling if we don't have FCOMI.
5517-
if (Subtarget->hasCMov())
5517+
if (Subtarget->hasCMOV())
55185518
break;
55195519

55205520
bool IsSignaling = Node->getOpcode() == X86ISD::STRICT_FCMPS;

llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -200,7 +200,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
200200
}
201201

202202
// Integer absolute.
203-
if (Subtarget.hasCMov()) {
203+
if (Subtarget.hasCMOV()) {
204204
setOperationAction(ISD::ABS , MVT::i16 , Custom);
205205
setOperationAction(ISD::ABS , MVT::i32 , Custom);
206206
if (Subtarget.is64Bit())
@@ -23466,7 +23466,7 @@ X86TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
2346623466

2346723467
// Only perform this transform if CMOV is supported otherwise the select
2346823468
// below will become a branch.
23469-
if (!Subtarget.hasCMov())
23469+
if (!Subtarget.hasCMOV())
2347023470
return SDValue();
2347123471

2347223472
// fold (sdiv X, pow2)
@@ -24656,7 +24656,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2465624656
return (Op1.getOpcode() == ISD::CTTZ_ZERO_UNDEF && Op1.hasOneUse() &&
2465724657
Op1.getOperand(0) == CmpOp0 && isAllOnesConstant(Op2));
2465824658
};
24659-
if (Subtarget.hasCMov() && (VT == MVT::i32 || VT == MVT::i64) &&
24659+
if (Subtarget.hasCMOV() && (VT == MVT::i32 || VT == MVT::i64) &&
2466024660
((CondCode == X86::COND_NE && MatchFFSMinus1(Op1, Op2)) ||
2466124661
(CondCode == X86::COND_E && MatchFFSMinus1(Op2, Op1)))) {
2466224662
// Keep Cmp.
@@ -24684,7 +24684,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2468424684
DAG.getTargetConstant(X86::COND_B, DL, MVT::i8),
2468524685
Sub.getValue(1));
2468624686
return DAG.getNode(ISD::OR, DL, VT, SBB, Y);
24687-
} else if (!Subtarget.hasCMov() && CondCode == X86::COND_E &&
24687+
} else if (!Subtarget.hasCMOV() && CondCode == X86::COND_E &&
2468824688
Cmp.getOperand(0).getOpcode() == ISD::AND &&
2468924689
isOneConstant(Cmp.getOperand(0).getOperand(1))) {
2469024690
SDValue Src1, Src2;
@@ -24739,7 +24739,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2473924739
SDValue Cmp = Cond.getOperand(1);
2474024740
bool IllegalFPCMov = false;
2474124741
if (VT.isFloatingPoint() && !VT.isVector() &&
24742-
!isScalarFPTypeInSSEReg(VT) && Subtarget.hasCMov()) // FPStack?
24742+
!isScalarFPTypeInSSEReg(VT) && Subtarget.hasCMOV()) // FPStack?
2474324743
IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
2474424744

2474524745
if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
@@ -24820,7 +24820,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2482024820
// legal, but EmitLoweredSelect() can not deal with these extensions
2482124821
// being inserted between two CMOV's. (in i16 case too TBN)
2482224822
// https://bugs.llvm.org/show_bug.cgi?id=40974
24823-
if ((Op.getValueType() == MVT::i8 && Subtarget.hasCMov()) ||
24823+
if ((Op.getValueType() == MVT::i8 && Subtarget.hasCMOV()) ||
2482424824
(Op.getValueType() == MVT::i16 && !X86::mayFoldLoad(Op1, Subtarget) &&
2482524825
!X86::mayFoldLoad(Op2, Subtarget))) {
2482624826
Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op1);
@@ -45100,7 +45100,7 @@ static SDValue combineCMov(SDNode *N, SelectionDAG &DAG,
4510045100
if (!(FalseOp.getValueType() == MVT::f80 ||
4510145101
(FalseOp.getValueType() == MVT::f64 && !Subtarget.hasSSE2()) ||
4510245102
(FalseOp.getValueType() == MVT::f32 && !Subtarget.hasSSE1())) ||
45103-
!Subtarget.hasCMov() || hasFPCMov(CC)) {
45103+
!Subtarget.hasCMOV() || hasFPCMov(CC)) {
4510445104
SDValue Ops[] = {FalseOp, TrueOp, DAG.getTargetConstant(CC, DL, MVT::i8),
4510545105
Flags};
4510645106
return DAG.getNode(X86ISD::CMOV, DL, N->getValueType(0), Ops);

llvm/lib/Target/X86/X86InstrCMovSetCC.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@
1414

1515
// CMOV instructions.
1616
let isCodeGenOnly = 1, ForceDisassemble = 1 in {
17-
let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
17+
let Uses = [EFLAGS], Predicates = [HasCMOV], Constraints = "$src1 = $dst",
1818
isCommutable = 1, SchedRW = [WriteCMOV] in {
1919
def CMOV16rr
2020
: I<0x40, MRMSrcRegCC, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, ccode:$cond),
@@ -35,7 +35,7 @@ let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
3535
(X86cmov GR64:$src1, GR64:$src2, timm:$cond, EFLAGS))]>, TB;
3636
}
3737

38-
let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
38+
let Uses = [EFLAGS], Predicates = [HasCMOV], Constraints = "$src1 = $dst",
3939
SchedRW = [WriteCMOV.Folded, WriteCMOV.ReadAfterFold] in {
4040
def CMOV16rm
4141
: I<0x40, MRMSrcMemCC, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2, ccode:$cond),
@@ -52,7 +52,7 @@ let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
5252
"cmov${cond}{q}\t{$src2, $dst|$dst, $src2}",
5353
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
5454
timm:$cond, EFLAGS))]>, TB;
55-
} // Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst"
55+
} // Uses = [EFLAGS], Predicates = [HasCMOV], Constraints = "$src1 = $dst"
5656
} // isCodeGenOnly = 1, ForceDisassemble = 1
5757

5858
def inv_cond_XFORM : SDNodeXForm<imm, [{
@@ -63,7 +63,7 @@ def inv_cond_XFORM : SDNodeXForm<imm, [{
6363

6464
// Conditional moves with folded loads with operands swapped and conditions
6565
// inverted.
66-
let Predicates = [HasCMov] in {
66+
let Predicates = [HasCMOV] in {
6767
def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, timm:$cond, EFLAGS),
6868
(CMOV16rm GR16:$src2, addr:$src1, (inv_cond_XFORM timm:$cond))>;
6969
def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, timm:$cond, EFLAGS),

llvm/lib/Target/X86/X86InstrCompiler.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -544,10 +544,10 @@ let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS] in {
544544
// i8 register pressure.
545545
defm _GR8 : CMOVrr_PSEUDO<GR8, i8>;
546546

547-
let Predicates = [NoCMov] in {
547+
let Predicates = [NoCMOV] in {
548548
defm _GR32 : CMOVrr_PSEUDO<GR32, i32>;
549549
defm _GR16 : CMOVrr_PSEUDO<GR16, i16>;
550-
} // Predicates = [NoCMov]
550+
} // Predicates = [NoCMOV]
551551

552552
// fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
553553
// SSE1/SSE2.

llvm/lib/Target/X86/X86InstrFPStack.td

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -423,9 +423,9 @@ def FBSTPm : FPI<0xDF, MRM6m, (outs), (ins f80mem:$dst), "fbstp\t$dst">;
423423

424424
// Floating point cmovs.
425425
class FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
426-
FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32, HasCMov]>;
426+
FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32, HasCMOV]>;
427427
class FpIf64CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
428-
FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64, HasCMov]>;
428+
FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64, HasCMOV]>;
429429

430430
multiclass FPCMov<PatLeaf cc> {
431431
def _Fp32 : FpIf32CMov<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2),
@@ -440,7 +440,7 @@ multiclass FPCMov<PatLeaf cc> {
440440
CondMovFP,
441441
[(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2,
442442
cc, EFLAGS))]>,
443-
Requires<[HasCMov]>;
443+
Requires<[HasCMOV]>;
444444
}
445445

446446
let SchedRW = [WriteFCMOV] in {
@@ -455,7 +455,7 @@ defm CMOVNE : FPCMov<X86_COND_NE>;
455455
defm CMOVNP : FPCMov<X86_COND_NP>;
456456
} // Uses = [EFLAGS], Constraints = "$src1 = $dst"
457457

458-
let Predicates = [HasCMov] in {
458+
let Predicates = [HasCMOV] in {
459459
// These are not factored because there's no clean way to pass DA/DB.
460460
def CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RSTi:$op),
461461
"fcmovb\t{$op, %st|st, $op}">;
@@ -473,7 +473,7 @@ def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RSTi:$op),
473473
"fcmovne\t{$op, %st|st, $op}">;
474474
def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RSTi:$op),
475475
"fcmovnu\t{$op, %st|st, $op}">;
476-
} // Predicates = [HasCMov]
476+
} // Predicates = [HasCMOV]
477477
} // SchedRW
478478

479479
let mayRaiseFPException = 1 in {
@@ -664,22 +664,22 @@ let SchedRW = [WriteFCom], mayRaiseFPException = 1 in {
664664
let Defs = [EFLAGS, FPSW], Uses = [FPCW] in {
665665
def UCOM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
666666
[(set EFLAGS, (X86any_fcmp RFP32:$lhs, RFP32:$rhs))]>,
667-
Requires<[FPStackf32, HasCMov]>;
667+
Requires<[FPStackf32, HasCMOV]>;
668668
def UCOM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
669669
[(set EFLAGS, (X86any_fcmp RFP64:$lhs, RFP64:$rhs))]>,
670-
Requires<[FPStackf64, HasCMov]>;
670+
Requires<[FPStackf64, HasCMOV]>;
671671
def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
672672
[(set EFLAGS, (X86any_fcmp RFP80:$lhs, RFP80:$rhs))]>,
673-
Requires<[HasCMov]>;
673+
Requires<[HasCMOV]>;
674674
def COM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
675675
[(set EFLAGS, (X86strict_fcmps RFP32:$lhs, RFP32:$rhs))]>,
676-
Requires<[FPStackf32, HasCMov]>;
676+
Requires<[FPStackf32, HasCMOV]>;
677677
def COM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
678678
[(set EFLAGS, (X86strict_fcmps RFP64:$lhs, RFP64:$rhs))]>,
679-
Requires<[FPStackf64, HasCMov]>;
679+
Requires<[FPStackf64, HasCMOV]>;
680680
def COM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
681681
[(set EFLAGS, (X86strict_fcmps RFP80:$lhs, RFP80:$rhs))]>,
682-
Requires<[HasCMov]>;
682+
Requires<[HasCMOV]>;
683683
}
684684

685685
let Uses = [ST0, FPCW] in {

llvm/lib/Target/X86/X86InstrInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3463,7 +3463,7 @@ bool X86InstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
34633463
Register FalseReg, int &CondCycles,
34643464
int &TrueCycles, int &FalseCycles) const {
34653465
// Not all subtargets have cmov instructions.
3466-
if (!Subtarget.hasCMov())
3466+
if (!Subtarget.hasCMOV())
34673467
return false;
34683468
if (Cond.size() != 1)
34693469
return false;

llvm/lib/Target/X86/X86InstrInfo.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -875,8 +875,8 @@ def relocImm : ComplexPattern<iAny, 1, "selectRelocImm",
875875
// X86 Instruction Predicate Definitions.
876876
def TruePredicate : Predicate<"true">;
877877

878-
def HasCMov : Predicate<"Subtarget->hasCMov()">;
879-
def NoCMov : Predicate<"!Subtarget->hasCMov()">;
878+
def HasCMOV : Predicate<"Subtarget->hasCMOV()">;
879+
def NoCMOV : Predicate<"!Subtarget->hasCMOV()">;
880880

881881
def HasMMX : Predicate<"Subtarget->hasMMX()">;
882882
def Has3DNow : Predicate<"Subtarget->hasThreeDNow()">;

llvm/lib/Target/X86/X86Subtarget.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -359,7 +359,7 @@ const RegisterBankInfo *X86Subtarget::getRegBankInfo() const {
359359
}
360360

361361
bool X86Subtarget::enableEarlyIfConversion() const {
362-
return hasCMov() && X86EarlyIfConv;
362+
return hasCMOV() && X86EarlyIfConv;
363363
}
364364

365365
void X86Subtarget::getPostRAMutations(

llvm/lib/Target/X86/X86Subtarget.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -636,7 +636,7 @@ class X86Subtarget final : public X86GenSubtargetInfo {
636636
bool hasNOPL() const { return HasNOPL; }
637637
// SSE codegen depends on cmovs, and all SSE1+ processors support them.
638638
// All 64-bit processors support cmov.
639-
bool hasCMov() const { return HasCMOV || X86SSELevel >= SSE1 || is64Bit(); }
639+
bool hasCMOV() const { return HasCMOV || X86SSELevel >= SSE1 || is64Bit(); }
640640
bool hasSSE1() const { return X86SSELevel >= SSE1; }
641641
bool hasSSE2() const { return X86SSELevel >= SSE2; }
642642
bool hasSSE3() const { return X86SSELevel >= SSE3; }

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