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Merge commit 'b5cbd9628e93' from llvm.org/main into next
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6 files changed

+58
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‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Lines changed: 22 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -3201,20 +3201,17 @@ bool RISCVDAGToDAGISel::doPeepholeMaskedRVV(SDNode *N) {
32013201
// not the pseudo name. That is, a TA VMERGE_VVM can be either the _TU pseudo
32023202
// form with an IMPLICIT_DEF passthrough operand or the unsuffixed (TA) pseudo
32033203
// form.
3204-
bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N, bool IsTA) {
3205-
3206-
SDValue Merge;
3207-
if (!IsTA)
3208-
Merge = N->getOperand(0);
3209-
unsigned Offset = IsTA ? 0 : 1;
3210-
SDValue False = N->getOperand(0 + Offset);
3211-
SDValue True = N->getOperand(1 + Offset);
3212-
SDValue Mask = N->getOperand(2 + Offset);
3213-
SDValue VL = N->getOperand(3 + Offset);
3214-
3215-
// For the _TU psuedo form, we require that either merge and false
3216-
// are the same, or that merge is undefined.
3217-
if (!IsTA && Merge != False && !isImplicitDef(Merge))
3204+
bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
3205+
3206+
SDValue Merge = N->getOperand(0);
3207+
SDValue False = N->getOperand(1);
3208+
SDValue True = N->getOperand(2);
3209+
SDValue Mask = N->getOperand(3);
3210+
SDValue VL = N->getOperand(4);
3211+
3212+
// We require that either merge and false are the same, or that merge
3213+
// is undefined.
3214+
if (Merge != False && !isImplicitDef(Merge))
32183215
return false;
32193216

32203217
assert(True.getResNo() == 0 &&
@@ -3247,7 +3244,7 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N, bool IsTA) {
32473244
// The vmerge instruction must be TU.
32483245
// FIXME: This could be relaxed, but we need to handle the policy for the
32493246
// resulting op correctly.
3250-
if (IsTA || isImplicitDef(Merge))
3247+
if (isImplicitDef(Merge))
32513248
return false;
32523249
SDValue MergeOpTrue = True->getOperand(0);
32533250
// Both the vmerge instruction and the True instruction must have the same
@@ -3259,7 +3256,7 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N, bool IsTA) {
32593256
if (IsMasked) {
32603257
assert(HasTiedDest && "Expected tied dest");
32613258
// The vmerge instruction must be TU.
3262-
if (IsTA || isImplicitDef(Merge))
3259+
if (isImplicitDef(Merge))
32633260
return false;
32643261
// The vmerge instruction must have an all 1s mask since we're going to keep
32653262
// the mask from the True instruction.
@@ -3325,7 +3322,7 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N, bool IsTA) {
33253322
"Expected instructions with mask have a tied dest.");
33263323
#endif
33273324

3328-
uint64_t Policy = (IsTA || isImplicitDef(N->getOperand(0))) ?
3325+
uint64_t Policy = isImplicitDef(N->getOperand(0)) ?
33293326
RISCVII::TAIL_AGNOSTIC : /*TUMU*/ 0;
33303327
SDValue PolicyOp =
33313328
CurDAG->getTargetConstant(Policy, DL, Subtarget->getXLenVT());
@@ -3367,17 +3364,17 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N, bool IsTA) {
33673364
return true;
33683365
}
33693366

3370-
// Transform (VMERGE_VVM_<LMUL>_TU false, false, true, allones, vl, sew) to
3371-
// (VMV_V_V_<LMUL>_TU false, true, vl, sew). It may decrease uses of VMSET.
3367+
// Transform (VMERGE_VVM_<LMUL> false, false, true, allones, vl, sew) to
3368+
// (VMV_V_V_<LMUL> false, true, vl, sew). It may decrease uses of VMSET.
33723369
bool RISCVDAGToDAGISel::performVMergeToVMv(SDNode *N) {
33733370
#define CASE_VMERGE_TO_VMV(lmul) \
3374-
case RISCV::PseudoVMERGE_VVM_##lmul##_TU: \
3371+
case RISCV::PseudoVMERGE_VVM_##lmul: \
33753372
NewOpc = RISCV::PseudoVMV_V_V_##lmul; \
33763373
break;
33773374
unsigned NewOpc;
33783375
switch (N->getMachineOpcode()) {
33793376
default:
3380-
llvm_unreachable("Expected VMERGE_VVM_<LMUL>_TU instruction.");
3377+
llvm_unreachable("Expected VMERGE_VVM_<LMUL> instruction.");
33813378
CASE_VMERGE_TO_VMV(MF8)
33823379
CASE_VMERGE_TO_VMV(MF4)
33833380
CASE_VMERGE_TO_VMV(MF2)
@@ -3410,17 +3407,7 @@ bool RISCVDAGToDAGISel::doPeepholeMergeVVMFold() {
34103407
if (N->use_empty() || !N->isMachineOpcode())
34113408
continue;
34123409

3413-
auto IsVMergeTU = [](unsigned Opcode) {
3414-
return Opcode == RISCV::PseudoVMERGE_VVM_MF8_TU ||
3415-
Opcode == RISCV::PseudoVMERGE_VVM_MF4_TU ||
3416-
Opcode == RISCV::PseudoVMERGE_VVM_MF2_TU ||
3417-
Opcode == RISCV::PseudoVMERGE_VVM_M1_TU ||
3418-
Opcode == RISCV::PseudoVMERGE_VVM_M2_TU ||
3419-
Opcode == RISCV::PseudoVMERGE_VVM_M4_TU ||
3420-
Opcode == RISCV::PseudoVMERGE_VVM_M8_TU;
3421-
};
3422-
3423-
auto IsVMergeTA = [](unsigned Opcode) {
3410+
auto IsVMerge = [](unsigned Opcode) {
34243411
return Opcode == RISCV::PseudoVMERGE_VVM_MF8 ||
34253412
Opcode == RISCV::PseudoVMERGE_VVM_MF4 ||
34263413
Opcode == RISCV::PseudoVMERGE_VVM_MF2 ||
@@ -3431,9 +3418,9 @@ bool RISCVDAGToDAGISel::doPeepholeMergeVVMFold() {
34313418
};
34323419

34333420
unsigned Opc = N->getMachineOpcode();
3434-
if (IsVMergeTU(Opc) || IsVMergeTA(Opc))
3435-
MadeChange |= performCombineVMergeAndVOps(N, IsVMergeTA(Opc));
3436-
if (IsVMergeTU(Opc) && N->getOperand(0) == N->getOperand(1))
3421+
if (IsVMerge(Opc))
3422+
MadeChange |= performCombineVMergeAndVOps(N);
3423+
if (IsVMerge(Opc) && N->getOperand(0) == N->getOperand(1))
34373424
MadeChange |= performVMergeToVMv(N);
34383425
}
34393426
return MadeChange;

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -182,7 +182,7 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
182182
bool doPeepholeMaskedRVV(SDNode *Node);
183183
bool doPeepholeMergeVVMFold();
184184
bool performVMergeToVMv(SDNode *N);
185-
bool performCombineVMergeAndVOps(SDNode *N, bool IsTA);
185+
bool performCombineVMergeAndVOps(SDNode *N);
186186
};
187187

188188
namespace RISCV {

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 10 additions & 57 deletions
Original file line numberDiff line numberDiff line change
@@ -2108,7 +2108,7 @@ multiclass VPseudoBinaryV_VM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
21082108
}
21092109

21102110
multiclass VPseudoTiedBinaryV_VM<LMULInfo m> {
2111-
def "_VVM" # "_" # m.MX # "_TU" :
2111+
def "_VVM" # "_" # m.MX:
21122112
VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
21132113
m.vrclass, m.vrclass, m, 1, "">;
21142114
}
@@ -2123,7 +2123,7 @@ multiclass VPseudoBinaryV_XM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
21232123
}
21242124

21252125
multiclass VPseudoTiedBinaryV_XM<LMULInfo m> {
2126-
def "_VXM" # "_" # m.MX # "_TU":
2126+
def "_VXM" # "_" # m.MX:
21272127
VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
21282128
m.vrclass, GPR, m, 1, "">;
21292129
}
@@ -2136,12 +2136,7 @@ multiclass VPseudoVMRG_FM {
21362136
defvar ReadVFMergeV_MX = !cast<SchedRead>("ReadVFMergeV_" # mx);
21372137
defvar ReadVFMergeF_MX = !cast<SchedRead>("ReadVFMergeF_" # mx);
21382138

2139-
def "_V" # f.FX # "M_" # mx :
2140-
VPseudoBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
2141-
m.vrclass, f.fprclass, m, /*CarryIn=*/1, "">,
2142-
Sched<[WriteVFMergeV_MX, ReadVFMergeV_MX, ReadVFMergeF_MX, ReadVMask]>;
2143-
// Tied version to allow codegen control over the tail elements
2144-
def "_V" # f.FX # "M_" # mx # "_TU":
2139+
def "_V" # f.FX # "M_" # mx:
21452140
VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
21462141
m.vrclass, f.fprclass, m, /*CarryIn=*/1, "">,
21472142
Sched<[WriteVFMergeV_MX, ReadVFMergeV_MX, ReadVFMergeF_MX, ReadVMask]>;
@@ -2159,7 +2154,7 @@ multiclass VPseudoBinaryV_IM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
21592154
}
21602155

21612156
multiclass VPseudoTiedBinaryV_IM<LMULInfo m> {
2162-
def "_VIM" # "_" # m.MX # "_TU":
2157+
def "_VIM" # "_" # m.MX:
21632158
VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
21642159
m.vrclass, simm5, m, 1, "">;
21652160
}
@@ -2833,28 +2828,15 @@ multiclass VPseudoVMRG_VM_XM_IM {
28332828
defvar ReadVIMergeV_MX = !cast<SchedRead>("ReadVIMergeV_" # mx);
28342829
defvar ReadVIMergeX_MX = !cast<SchedRead>("ReadVIMergeX_" # mx);
28352830

2836-
def "_VVM" # "_" # m.MX :
2837-
VPseudoBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
2838-
m.vrclass, m.vrclass, m, 1, "">,
2839-
Sched<[WriteVIMergeV_MX, ReadVIMergeV_MX, ReadVIMergeV_MX, ReadVMask]>;
2840-
def "_VXM" # "_" # m.MX :
2841-
VPseudoBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
2842-
m.vrclass, GPR, m, 1, "">,
2843-
Sched<[WriteVIMergeX_MX, ReadVIMergeV_MX, ReadVIMergeX_MX, ReadVMask]>;
2844-
def "_VIM" # "_" # m.MX :
2845-
VPseudoBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
2846-
m.vrclass, simm5, m, 1, "">,
2847-
Sched<[WriteVIMergeI_MX, ReadVIMergeV_MX, ReadVMask]>;
2848-
// Tied versions to allow codegen control over the tail elements
2849-
def "_VVM" # "_" # m.MX # "_TU" :
2831+
def "_VVM" # "_" # m.MX:
28502832
VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
28512833
m.vrclass, m.vrclass, m, 1, "">,
28522834
Sched<[WriteVIMergeV_MX, ReadVIMergeV_MX, ReadVIMergeV_MX, ReadVMask]>;
2853-
def "_VXM" # "_" # m.MX # "_TU":
2835+
def "_VXM" # "_" # m.MX:
28542836
VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
28552837
m.vrclass, GPR, m, 1, "">,
28562838
Sched<[WriteVIMergeX_MX, ReadVIMergeV_MX, ReadVIMergeX_MX, ReadVMask]>;
2857-
def "_VIM" # "_" # m.MX # "_TU":
2839+
def "_VIM" # "_" # m.MX:
28582840
VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
28592841
m.vrclass, simm5, m, 1, "">,
28602842
Sched<[WriteVIMergeI_MX, ReadVIMergeV_MX, ReadVMask]>;
@@ -2870,13 +2852,6 @@ multiclass VPseudoVCALU_VM_XM_IM {
28702852
defvar ReadVICALUV_MX = !cast<SchedRead>("ReadVICALUV_" # mx);
28712853
defvar ReadVICALUX_MX = !cast<SchedRead>("ReadVICALUX_" # mx);
28722854

2873-
defm "" : VPseudoBinaryV_VM<m>,
2874-
Sched<[WriteVICALUV_MX, ReadVICALUV_MX, ReadVICALUV_MX, ReadVMask]>;
2875-
defm "" : VPseudoBinaryV_XM<m>,
2876-
Sched<[WriteVICALUX_MX, ReadVICALUV_MX, ReadVICALUX_MX, ReadVMask]>;
2877-
defm "" : VPseudoBinaryV_IM<m>,
2878-
Sched<[WriteVICALUI_MX, ReadVICALUV_MX, ReadVMask]>;
2879-
// Tied versions to allow codegen control over the tail elements
28802855
defm "" : VPseudoTiedBinaryV_VM<m>,
28812856
Sched<[WriteVICALUV_MX, ReadVICALUV_MX, ReadVICALUV_MX, ReadVMask]>;
28822857
defm "" : VPseudoTiedBinaryV_XM<m>,
@@ -2894,11 +2869,6 @@ multiclass VPseudoVCALU_VM_XM {
28942869
defvar ReadVICALUV_MX = !cast<SchedRead>("ReadVICALUV_" # mx);
28952870
defvar ReadVICALUX_MX = !cast<SchedRead>("ReadVICALUX_" # mx);
28962871

2897-
defm "" : VPseudoBinaryV_VM<m>,
2898-
Sched<[WriteVICALUV_MX, ReadVICALUV_MX, ReadVICALUV_MX, ReadVMask]>;
2899-
defm "" : VPseudoBinaryV_XM<m>,
2900-
Sched<[WriteVICALUX_MX, ReadVICALUV_MX, ReadVICALUX_MX, ReadVMask]>;
2901-
// Tied versions to allow codegen control over the tail elements
29022872
defm "" : VPseudoTiedBinaryV_VM<m>,
29032873
Sched<[WriteVICALUV_MX, ReadVICALUV_MX, ReadVICALUV_MX, ReadVMask]>;
29042874
defm "" : VPseudoTiedBinaryV_XM<m>,
@@ -4410,23 +4380,13 @@ multiclass VPatBinaryCarryInTAIL<string intrinsic,
44104380
VReg result_reg_class,
44114381
VReg op1_reg_class,
44124382
DAGOperand op2_kind> {
4413-
def : Pat<(result_type (!cast<Intrinsic>(intrinsic)
4414-
(result_type undef),
4415-
(op1_type op1_reg_class:$rs1),
4416-
(op2_type op2_kind:$rs2),
4417-
(mask_type V0),
4418-
VLOpFrag)),
4419-
(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX)
4420-
(op1_type op1_reg_class:$rs1),
4421-
(op2_type op2_kind:$rs2),
4422-
(mask_type V0), GPR:$vl, sew)>;
44234383
def : Pat<(result_type (!cast<Intrinsic>(intrinsic)
44244384
(result_type result_reg_class:$merge),
44254385
(op1_type op1_reg_class:$rs1),
44264386
(op2_type op2_kind:$rs2),
44274387
(mask_type V0),
44284388
VLOpFrag)),
4429-
(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_TU")
4389+
(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX)
44304390
(result_type result_reg_class:$merge),
44314391
(op1_type op1_reg_class:$rs1),
44324392
(op2_type op2_kind:$rs2),
@@ -6486,19 +6446,12 @@ foreach vti = AllFloatVectors in {
64866446
foreach fvti = AllFloatVectors in {
64876447
defvar instr = !cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX);
64886448
let Predicates = GetVTypePredicates<fvti>.Predicates in
6489-
def : Pat<(fvti.Vector (int_riscv_vfmerge (fvti.Vector undef),
6490-
(fvti.Vector fvti.RegClass:$rs2),
6491-
(fvti.Scalar (fpimm0)),
6492-
(fvti.Mask V0), VLOpFrag)),
6493-
(instr fvti.RegClass:$rs2, 0, (fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>;
6494-
defvar instr_tu = !cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX#"_TU");
6495-
let Predicates = GetVTypePredicates<fvti>.Predicates in
64966449
def : Pat<(fvti.Vector (int_riscv_vfmerge (fvti.Vector fvti.RegClass:$merge),
64976450
(fvti.Vector fvti.RegClass:$rs2),
64986451
(fvti.Scalar (fpimm0)),
64996452
(fvti.Mask V0), VLOpFrag)),
6500-
(instr_tu fvti.RegClass:$merge, fvti.RegClass:$rs2, 0,
6501-
(fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>;
6453+
(instr fvti.RegClass:$merge, fvti.RegClass:$rs2, 0,
6454+
(fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>;
65026455
}
65036456

65046457
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -902,20 +902,20 @@ foreach vti = AllIntegerVectors in {
902902
let Predicates = GetVTypePredicates<vti>.Predicates in {
903903
def : Pat<(vti.Vector (vselect (vti.Mask V0), vti.RegClass:$rs1,
904904
vti.RegClass:$rs2)),
905-
(!cast<Instruction>("PseudoVMERGE_VVM_"#vti.LMul.MX#"_TU")
905+
(!cast<Instruction>("PseudoVMERGE_VVM_"#vti.LMul.MX)
906906
(vti.Vector (IMPLICIT_DEF)),
907907
vti.RegClass:$rs2, vti.RegClass:$rs1, (vti.Mask V0),
908908
vti.AVL, vti.Log2SEW)>;
909909

910910
def : Pat<(vti.Vector (vselect (vti.Mask V0), (SplatPat XLenVT:$rs1),
911911
vti.RegClass:$rs2)),
912-
(!cast<Instruction>("PseudoVMERGE_VXM_"#vti.LMul.MX#"_TU")
912+
(!cast<Instruction>("PseudoVMERGE_VXM_"#vti.LMul.MX)
913913
(vti.Vector (IMPLICIT_DEF)),
914914
vti.RegClass:$rs2, GPR:$rs1, (vti.Mask V0), vti.AVL, vti.Log2SEW)>;
915915

916916
def : Pat<(vti.Vector (vselect (vti.Mask V0), (SplatPat_simm5 simm5:$rs1),
917917
vti.RegClass:$rs2)),
918-
(!cast<Instruction>("PseudoVMERGE_VIM_"#vti.LMul.MX#"_TU")
918+
(!cast<Instruction>("PseudoVMERGE_VIM_"#vti.LMul.MX)
919919
(vti.Vector (IMPLICIT_DEF)),
920920
vti.RegClass:$rs2, simm5:$rs1, (vti.Mask V0), vti.AVL, vti.Log2SEW)>;
921921
}
@@ -1125,15 +1125,15 @@ foreach fvti = AllFloatVectors in {
11251125
let Predicates = GetVTypePredicates<fvti>.Predicates in {
11261126
def : Pat<(fvti.Vector (vselect (fvti.Mask V0), fvti.RegClass:$rs1,
11271127
fvti.RegClass:$rs2)),
1128-
(!cast<Instruction>("PseudoVMERGE_VVM_"#fvti.LMul.MX#"_TU")
1128+
(!cast<Instruction>("PseudoVMERGE_VVM_"#fvti.LMul.MX)
11291129
(fvti.Vector (IMPLICIT_DEF)),
11301130
fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask V0),
11311131
fvti.AVL, fvti.Log2SEW)>;
11321132

11331133
def : Pat<(fvti.Vector (vselect (fvti.Mask V0),
11341134
(SplatFPOp fvti.ScalarRegClass:$rs1),
11351135
fvti.RegClass:$rs2)),
1136-
(!cast<Instruction>("PseudoVFMERGE_V"#fvti.ScalarSuffix#"M_"#fvti.LMul.MX#"_TU")
1136+
(!cast<Instruction>("PseudoVFMERGE_V"#fvti.ScalarSuffix#"M_"#fvti.LMul.MX)
11371137
(fvti.Vector (IMPLICIT_DEF)),
11381138
fvti.RegClass:$rs2,
11391139
(fvti.Scalar fvti.ScalarRegClass:$rs1),
@@ -1142,7 +1142,7 @@ foreach fvti = AllFloatVectors in {
11421142
def : Pat<(fvti.Vector (vselect (fvti.Mask V0),
11431143
(SplatFPOp (fvti.Scalar fpimm0)),
11441144
fvti.RegClass:$rs2)),
1145-
(!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX#"_TU")
1145+
(!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX)
11461146
(fvti.Vector (IMPLICIT_DEF)),
11471147
fvti.RegClass:$rs2, 0, (fvti.Mask V0), fvti.AVL, fvti.Log2SEW)>;
11481148
}

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