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[ARM][Thumb2] Allow 2-operand variants of [us]div (llvm#119976)
Fixes llvm#119963
1 parent 3b17d04 commit 9455ea7

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+49
-3
lines changed

4 files changed

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‎llvm/lib/Target/ARM/ARMInstrInfo.td

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@@ -4765,6 +4765,7 @@ def : ARMV6Pat<(int_arm_smusdx GPRnopc:$Rn, GPRnopc:$Rm),
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//===----------------------------------------------------------------------===//
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// Division Instructions (ARMv7-A with virtualization extension)
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//
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let TwoOperandAliasConstraint = "$Rn = $Rd" in {
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def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
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"sdiv", "\t$Rd, $Rn, $Rm",
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[(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
@@ -4776,6 +4777,7 @@ def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
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[(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
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Requires<[IsARM, HasDivideInARM]>,
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Sched<[WriteDIV]>;
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}
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//===----------------------------------------------------------------------===//
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// Misc. Arithmetic Instructions.

‎llvm/lib/Target/ARM/ARMInstrThumb2.td

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@@ -3300,6 +3300,7 @@ def : Thumb2DSPPat<(ARMSmlsldx rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi),
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// Division Instructions.
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// Signed and unsigned division on v7-M
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//
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let TwoOperandAliasConstraint = "$Rn = $Rd" in {
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def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
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"sdiv", "\t$Rd, $Rn, $Rm",
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[(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
@@ -3323,6 +3324,7 @@ def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
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let Inst{15-12} = 0b1111;
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let Inst{7-4} = 0b1111;
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}
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}
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//===----------------------------------------------------------------------===//
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// Misc. Arithmetic Instructions.

‎llvm/test/MC/ARM/idiv-2op.s

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@@ -0,0 +1,42 @@
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@ RUN: llvm-mc -triple=armv7 -mcpu=cortex-m3 -show-encoding < %s 2>&1 | FileCheck -check-prefix M3-ARM %s
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@ RUN: llvm-mc -triple=thumbv7 -mcpu=cortex-m3 -show-encoding < %s 2>&1 | FileCheck -check-prefix M3-THUMB %s
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@ RUN: llvm-mc -triple=thumbv7 -mcpu=cortex-a15 -show-encoding < %s 2>&1 | FileCheck -check-prefix A15-THUMB %s
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@ RUN: llvm-mc -triple=thumbv7 -mcpu=cortex-a15 -show-encoding < %s 2>&1 | FileCheck -check-prefix A15-THUMB %s
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@ RUN: llvm-mc -triple=armv7 -mcpu=cortex-a15 -mattr=-hwdiv -show-encoding < %s 2>&1 | FileCheck -check-prefix A15-ARM-NOTHUMBHWDIV %s
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@ RUN: llvm-mc -triple=thumbv7 -mcpu=cortex-a15 -mattr=-hwdiv-arm -show-encoding < %s 2>&1 | FileCheck -check-prefix A15-THUMB-NOARMHWDIV %s
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@ RUN: llvm-mc -triple=armv8 -show-encoding < %s 2>&1 | FileCheck -check-prefix ARMV8 %s
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@ RUN: llvm-mc -triple=thumbv8 -show-encoding < %s 2>&1 | FileCheck -check-prefix THUMBV8 %s
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@ RUN: llvm-mc -triple=armv8 -mattr=-hwdiv -show-encoding < %s 2>&1 | FileCheck -check-prefix ARMV8-NOTHUMBHWDIV %s
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@ RUN: llvm-mc -triple=thumbv8 -mattr=-hwdiv-arm -show-encoding < %s 2>&1 | FileCheck -check-prefix THUMBV8-NOARMHWDIV %s
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sdiv r1, r2
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udiv r3, r4
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@ M3-ARM: sdiv r1, r1, r2 @ encoding: [0x91,0xfb,0xf2,0xf1]
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@ M3-ARM: udiv r3, r3, r4 @ encoding: [0xb3,0xfb,0xf4,0xf3]
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@ M3-THUMB: sdiv r1, r1, r2 @ encoding: [0x91,0xfb,0xf2,0xf1]
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@ M3-THUMB: udiv r3, r3, r4 @ encoding: [0xb3,0xfb,0xf4,0xf3]
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@ A15-ARM: sdiv r1, r1, r2 @ encoding: [0x11,0xf2,0x11,0xe7]
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@ A15-ARM: udiv r3, r3, r4 @ encoding: [0x13,0xf4,0x33,0xe7]
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@ A15-THUMB: sdiv r1, r1, r2 @ encoding: [0x91,0xfb,0xf2,0xf1]
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@ A15-THUMB: udiv r3, r3, r4 @ encoding: [0xb3,0xfb,0xf4,0xf3]
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@ A15-ARM-NOTHUMBHWDIV: sdiv r1, r1, r2 @ encoding: [0x11,0xf2,0x11,0xe7]
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@ A15-ARM-NOTHUMBHWDIV: udiv r3, r3, r4 @ encoding: [0x13,0xf4,0x33,0xe7]
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@ A15-THUMB-NOARMHWDIV: sdiv r1, r1, r2 @ encoding: [0x91,0xfb,0xf2,0xf1]
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@ A15-THUMB-NOARMHWDIV: udiv r3, r3, r4 @ encoding: [0xb3,0xfb,0xf4,0xf3]
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@ ARMV8: sdiv r1, r1, r2 @ encoding: [0x11,0xf2,0x11,0xe7]
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@ ARMV8: udiv r3, r3, r4 @ encoding: [0x13,0xf4,0x33,0xe7]
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@ THUMBV8: sdiv r1, r1, r2 @ encoding: [0x91,0xfb,0xf2,0xf1]
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@ THUMBV8: udiv r3, r3, r4 @ encoding: [0xb3,0xfb,0xf4,0xf3]
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@ ARMV8-NOTHUMBHWDIV: sdiv r1, r1, r2 @ encoding: [0x11,0xf2,0x11,0xe7]
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@ ARMV8-NOTHUMBHWDIV: udiv r3, r3, r4 @ encoding: [0x13,0xf4,0x33,0xe7]
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@ THUMBV8-NOARMHWDIV: sdiv r1, r1, r2 @ encoding: [0x91,0xfb,0xf2,0xf1]
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@ THUMBV8-NOARMHWDIV: udiv r3, r3, r4 @ encoding: [0xb3,0xfb,0xf4,0xf3]

‎llvm/test/MC/ARM/idiv.s

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@@ -8,7 +8,7 @@
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@ RUN: llvm-mc -triple=thumbv8 -show-encoding < %s 2>&1 | FileCheck -check-prefix THUMBV8 %s
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@ RUN: llvm-mc -triple=armv8 -mattr=-hwdiv -show-encoding < %s 2>&1 | FileCheck -check-prefix ARMV8-NOTHUMBHWDIV %s
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@ RUN: llvm-mc -triple=thumbv8 -mattr=-hwdiv-arm -show-encoding < %s 2>&1 | FileCheck -check-prefix THUMBV8-NOTHUMBHWDIV %s
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@ RUN: llvm-mc -triple=thumbv8 -mattr=-hwdiv-arm -show-encoding < %s 2>&1 | FileCheck -check-prefix THUMBV8-NOARMHWDIV %s
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sdiv r1, r2, r3
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udiv r3, r4, r5
@@ -29,5 +29,5 @@
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@ ARMV8-NOTHUMBHWDIV: sdiv r1, r2, r3 @ encoding: [0x12,0xf3,0x11,0xe7]
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@ ARMV8-NOTHUMBHWDIV: udiv r3, r4, r5 @ encoding: [0x14,0xf5,0x33,0xe7]
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@ THUMBV8-NOTHUMBHWDIV: sdiv r1, r2, r3 @ encoding: [0x92,0xfb,0xf3,0xf1]
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@ THUMBV8-NOTHUMBHWDIV: udiv r3, r4, r5 @ encoding: [0xb4,0xfb,0xf5,0xf3]
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@ THUMBV8-NOARMHWDIV: sdiv r1, r2, r3 @ encoding: [0x92,0xfb,0xf3,0xf1]
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@ THUMBV8-NOARMHWDIV: udiv r3, r4, r5 @ encoding: [0xb4,0xfb,0xf5,0xf3]

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