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Revert "[AArch64][GlobalISel] Widen G_ADD/G_MUL/G_OR/... element types if size < 8b"
This reverts commit 254e2ad. It contains broken test.
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8 files changed

+6
-965
lines changed

8 files changed

+6
-965
lines changed

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Lines changed: 0 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -128,21 +128,6 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
128128
.clampScalar(0, s32, s64)
129129
.clampNumElements(0, v2s32, v4s32)
130130
.clampNumElements(0, v2s64, v2s64)
131-
.minScalarOrEltIf(
132-
[=](const LegalityQuery &Query) {
133-
return Query.Types[0].getNumElements() <= 2;
134-
},
135-
0, s32)
136-
.minScalarOrEltIf(
137-
[=](const LegalityQuery &Query) {
138-
return Query.Types[0].getNumElements() <= 4;
139-
},
140-
0, s16)
141-
.minScalarOrEltIf(
142-
[=](const LegalityQuery &Query) {
143-
return Query.Types[0].getNumElements() <= 16;
144-
},
145-
0, s8)
146131
.moreElementsToNextPow2(0);
147132

148133
getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR})

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir

Lines changed: 0 additions & 155 deletions
Original file line numberDiff line numberDiff line change
@@ -282,159 +282,4 @@ body: |
282282
%2:_(<8 x s8>) = G_ADD %0, %1
283283
$d0 = COPY %2(<8 x s8>)
284284
RET_ReallyLR implicit $d0
285-
286-
...
287-
---
288-
name: add_v2s1
289-
tracksRegLiveness: true
290-
body: |
291-
bb.1:
292-
liveins: $d0, $d1, $d2, $d3
293-
294-
; CHECK-LABEL: name: add_v2s1
295-
; CHECK: liveins: $d0, $d1, $d2, $d3
296-
; CHECK-NEXT: {{ $}}
297-
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
298-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
299-
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $d2
300-
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s32>) = COPY $d3
301-
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY]](<2 x s32>), [[COPY1]]
302-
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY2]](<2 x s32>), [[COPY3]]
303-
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<2 x s32>) = G_ADD [[ICMP]], [[ICMP1]]
304-
; CHECK-NEXT: $d0 = COPY [[ADD]](<2 x s32>)
305-
; CHECK-NEXT: RET_ReallyLR implicit $d0
306-
%0:_(<2 x s32>) = COPY $d0
307-
%1:_(<2 x s32>) = COPY $d1
308-
%2:_(<2 x s32>) = COPY $d2
309-
%3:_(<2 x s32>) = COPY $d3
310-
%4:_(<2 x s1>) = G_ICMP intpred(eq), %0(<2 x s32>), %1
311-
%5:_(<2 x s1>) = G_ICMP intpred(eq), %2(<2 x s32>), %3
312-
%6:_(<2 x s1>) = G_ADD %4, %5
313-
%7:_(<2 x s32>) = G_ANYEXT %6
314-
$d0 = COPY %7:_(<2 x s32>)
315-
RET_ReallyLR implicit $d0
316-
...
317-
---
318-
name: add_v3s1
319-
tracksRegLiveness: true
320-
body: |
321-
bb.1:
322-
liveins: $b0, $b1, $b2
323-
324-
; CHECK-LABEL: name: add_v3s1
325-
; CHECK: liveins: $b0, $b1, $b2
326-
; CHECK-NEXT: {{ $}}
327-
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $b0
328-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s8) = COPY $b1
329-
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s8) = COPY $b2
330-
; CHECK-NEXT: [[ANYEXT0:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
331-
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY1]](s8)
332-
; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY2]](s8)
333-
; CHECK-NEXT: [[IMPLICIT_DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
334-
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[ANYEXT0]](s16), [[ANYEXT1]](s16), [[ANYEXT2]](s16), [[IMPLICIT_DEF]](s16)
335-
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<4 x s16>) = G_ADD [[BUILD_VECTOR]], [[BUILD_VECTOR]]
336-
; CHECK-NEXT: [[VAL0:%[0-9]+]]:_(s16), [[VAL1:%[0-9]+]]:_(s16), [[VAL2:%[0-9]+]]:_(s16), [[VAL3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[ADD]](<4 x s16>)
337-
; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[VAL0]](s16)
338-
; CHECK-NEXT: $b0 = COPY [[TRUNC3]](s8)
339-
; CHECK-NEXT: RET_ReallyLR implicit $b0
340-
%1:_(s8) = COPY $b0
341-
%2:_(s8) = COPY $b1
342-
%3:_(s8) = COPY $b2
343-
%4:_(<3 x s8>) = G_BUILD_VECTOR %1(s8), %2(s8), %3(s8)
344-
%0:_(<3 x s1>) = G_TRUNC %4(<3 x s8>)
345-
%5:_(<3 x s1>) = G_ADD %0, %0
346-
%7:_(<3 x s8>) = G_ANYEXT %5(<3 x s1>)
347-
%8:_(s8), %9:_(s8), %10:_(s8) = G_UNMERGE_VALUES %7(<3 x s8>)
348-
$b0 = COPY %8:_(s8)
349-
RET_ReallyLR implicit $b0
350-
...
351-
---
352-
name: add_v4s1
353-
tracksRegLiveness: true
354-
body: |
355-
bb.1:
356-
liveins: $d0, $d1, $d2, $d3
357-
358-
; CHECK-LABEL: name: add_v4s1
359-
; CHECK: liveins: $d0, $d1, $d2, $d3
360-
; CHECK-NEXT: {{ $}}
361-
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
362-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
363-
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $d2
364-
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x s16>) = COPY $d3
365-
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY]](<4 x s16>), [[COPY1]]
366-
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY2]](<4 x s16>), [[COPY3]]
367-
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<4 x s16>) = G_ADD [[ICMP]], [[ICMP1]]
368-
; CHECK-NEXT: $d0 = COPY [[ADD]](<4 x s16>)
369-
; CHECK-NEXT: RET_ReallyLR implicit $d0
370-
%0:_(<4 x s16>) = COPY $d0
371-
%1:_(<4 x s16>) = COPY $d1
372-
%2:_(<4 x s16>) = COPY $d2
373-
%3:_(<4 x s16>) = COPY $d3
374-
%4:_(<4 x s1>) = G_ICMP intpred(eq), %0(<4 x s16>), %1
375-
%5:_(<4 x s1>) = G_ICMP intpred(eq), %2(<4 x s16>), %3
376-
%6:_(<4 x s1>) = G_ADD %4, %5
377-
%7:_(<4 x s16>) = G_ANYEXT %6
378-
$d0 = COPY %7:_(<4 x s16>)
379-
RET_ReallyLR implicit $d0
380-
...
381-
---
382-
name: add_v8s1
383-
tracksRegLiveness: true
384-
body: |
385-
bb.1:
386-
liveins: $d0, $d1, $d2, $d3
387-
388-
; CHECK-LABEL: name: add_v8s1
389-
; CHECK: liveins: $d0, $d1, $d2, $d3
390-
; CHECK-NEXT: {{ $}}
391-
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
392-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
393-
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY $d2
394-
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<8 x s8>) = COPY $d3
395-
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY]](<8 x s8>), [[COPY1]]
396-
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY2]](<8 x s8>), [[COPY3]]
397-
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<8 x s8>) = G_ADD [[ICMP]], [[ICMP1]]
398-
; CHECK-NEXT: $d0 = COPY [[ADD]](<8 x s8>)
399-
; CHECK-NEXT: RET_ReallyLR implicit $d0
400-
%0:_(<8 x s8>) = COPY $d0
401-
%1:_(<8 x s8>) = COPY $d1
402-
%2:_(<8 x s8>) = COPY $d2
403-
%3:_(<8 x s8>) = COPY $d3
404-
%4:_(<8 x s1>) = G_ICMP intpred(eq), %0(<8 x s8>), %1
405-
%5:_(<8 x s1>) = G_ICMP intpred(eq), %2(<8 x s8>), %3
406-
%6:_(<8 x s1>) = G_ADD %4, %5
407-
%7:_(<8 x s8>) = G_ANYEXT %6
408-
$d0 = COPY %7:_(<8 x s8>)
409-
RET_ReallyLR implicit $d0
410-
...
411-
---
412-
name: add_v16s1
413-
tracksRegLiveness: true
414-
body: |
415-
bb.1:
416-
liveins: $q0, $q1, $q2, $q3
417-
418-
; CHECK-LABEL: name: add_v16s1
419-
; CHECK: liveins: $q0, $q1, $q2, $q3
420-
; CHECK-NEXT: {{ $}}
421-
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
422-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
423-
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY $q2
424-
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<16 x s8>) = COPY $q3
425-
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY]](<16 x s8>), [[COPY1]]
426-
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY2]](<16 x s8>), [[COPY3]]
427-
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[ICMP]], [[ICMP1]]
428-
; CHECK-NEXT: $q0 = COPY [[ADD]](<16 x s8>)
429-
; CHECK-NEXT: RET_ReallyLR implicit $q0
430-
%0:_(<16 x s8>) = COPY $q0
431-
%1:_(<16 x s8>) = COPY $q1
432-
%2:_(<16 x s8>) = COPY $q2
433-
%3:_(<16 x s8>) = COPY $q3
434-
%4:_(<16 x s1>) = G_ICMP intpred(eq), %0(<16 x s8>), %1
435-
%5:_(<16 x s1>) = G_ICMP intpred(eq), %2(<16 x s8>), %3
436-
%6:_(<16 x s1>) = G_ADD %4, %5
437-
%7:_(<16 x s8>) = G_ANYEXT %6
438-
$q0 = COPY %7:_(<16 x s8>)
439-
RET_ReallyLR implicit $q0
440285
...

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir

Lines changed: 0 additions & 156 deletions
Original file line numberDiff line numberDiff line change
@@ -158,159 +158,3 @@ body: |
158158
%and:_(s318) = G_AND %a, %b
159159
G_STORE %and(s318), %ptr(p0) :: (store (s318))
160160
RET_ReallyLR implicit $x0
161-
162-
...
163-
---
164-
name: and_v2s1
165-
tracksRegLiveness: true
166-
body: |
167-
bb.1:
168-
liveins: $d0, $d1, $d2, $d3
169-
170-
; CHECK-LABEL: name: and_v2s1
171-
; CHECK: liveins: $d0, $d1, $d2, $d3
172-
; CHECK-NEXT: {{ $}}
173-
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
174-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
175-
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $d2
176-
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s32>) = COPY $d3
177-
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY]](<2 x s32>), [[COPY1]]
178-
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY2]](<2 x s32>), [[COPY3]]
179-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[ICMP]], [[ICMP1]]
180-
; CHECK-NEXT: $d0 = COPY [[AND]](<2 x s32>)
181-
; CHECK-NEXT: RET_ReallyLR implicit $d0
182-
%0:_(<2 x s32>) = COPY $d0
183-
%1:_(<2 x s32>) = COPY $d1
184-
%2:_(<2 x s32>) = COPY $d2
185-
%3:_(<2 x s32>) = COPY $d3
186-
%4:_(<2 x s1>) = G_ICMP intpred(eq), %0(<2 x s32>), %1
187-
%5:_(<2 x s1>) = G_ICMP intpred(eq), %2(<2 x s32>), %3
188-
%6:_(<2 x s1>) = G_AND %4, %5
189-
%7:_(<2 x s32>) = G_ANYEXT %6
190-
$d0 = COPY %7:_(<2 x s32>)
191-
RET_ReallyLR implicit $d0
192-
...
193-
---
194-
name: and_v3s1
195-
tracksRegLiveness: true
196-
body: |
197-
bb.1:
198-
liveins: $b0, $b1, $b2
199-
200-
; CHECK-LABEL: name: and_v3s1
201-
; CHECK: liveins: $b0, $b1, $b2
202-
; CHECK-NEXT: {{ $}}
203-
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $b0
204-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s8) = COPY $b1
205-
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s8) = COPY $b2
206-
; CHECK-NEXT: [[ANYEXT0:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
207-
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY1]](s8)
208-
; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY2]](s8)
209-
; CHECK-NEXT: [[IMPLICIT_DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
210-
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[ANYEXT0]](s16), [[ANYEXT1]](s16), [[ANYEXT2]](s16), [[IMPLICIT_DEF]](s16)
211-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s16>) = G_AND [[BUILD_VECTOR]], [[BUILD_VECTOR]]
212-
; CHECK-NEXT: [[VAL0:%[0-9]+]]:_(s16), [[VAL1:%[0-9]+]]:_(s16), [[VAL2:%[0-9]+]]:_(s16), [[VAL3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[AND]](<4 x s16>)
213-
; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[VAL0]](s16)
214-
; CHECK-NEXT: $b0 = COPY [[TRUNC3]](s8)
215-
; CHECK-NEXT: RET_ReallyLR implicit $b0
216-
%1:_(s8) = COPY $b0
217-
%2:_(s8) = COPY $b1
218-
%3:_(s8) = COPY $b2
219-
%4:_(<3 x s8>) = G_BUILD_VECTOR %1(s8), %2(s8), %3(s8)
220-
%0:_(<3 x s1>) = G_TRUNC %4(<3 x s8>)
221-
%5:_(<3 x s1>) = G_AND %0, %0
222-
%7:_(<3 x s8>) = G_ANYEXT %5(<3 x s1>)
223-
%8:_(s8), %9:_(s8), %10:_(s8) = G_UNMERGE_VALUES %7(<3 x s8>)
224-
$b0 = COPY %8:_(s8)
225-
RET_ReallyLR implicit $b0
226-
...
227-
---
228-
name: and_v4s1
229-
tracksRegLiveness: true
230-
body: |
231-
bb.1:
232-
liveins: $d0, $d1, $d2, $d3
233-
234-
; CHECK-LABEL: name: and_v4s1
235-
; CHECK: liveins: $d0, $d1, $d2, $d3
236-
; CHECK-NEXT: {{ $}}
237-
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
238-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
239-
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $d2
240-
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x s16>) = COPY $d3
241-
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY]](<4 x s16>), [[COPY1]]
242-
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY2]](<4 x s16>), [[COPY3]]
243-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s16>) = G_AND [[ICMP]], [[ICMP1]]
244-
; CHECK-NEXT: $d0 = COPY [[AND]](<4 x s16>)
245-
; CHECK-NEXT: RET_ReallyLR implicit $d0
246-
%0:_(<4 x s16>) = COPY $d0
247-
%1:_(<4 x s16>) = COPY $d1
248-
%2:_(<4 x s16>) = COPY $d2
249-
%3:_(<4 x s16>) = COPY $d3
250-
%4:_(<4 x s1>) = G_ICMP intpred(eq), %0(<4 x s16>), %1
251-
%5:_(<4 x s1>) = G_ICMP intpred(eq), %2(<4 x s16>), %3
252-
%6:_(<4 x s1>) = G_AND %4, %5
253-
%7:_(<4 x s16>) = G_ANYEXT %6
254-
$d0 = COPY %7:_(<4 x s16>)
255-
RET_ReallyLR implicit $d0
256-
...
257-
---
258-
name: and_v8s1
259-
tracksRegLiveness: true
260-
body: |
261-
bb.1:
262-
liveins: $d0, $d1, $d2, $d3
263-
264-
; CHECK-LABEL: name: and_v8s1
265-
; CHECK: liveins: $d0, $d1, $d2, $d3
266-
; CHECK-NEXT: {{ $}}
267-
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
268-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
269-
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY $d2
270-
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<8 x s8>) = COPY $d3
271-
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY]](<8 x s8>), [[COPY1]]
272-
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY2]](<8 x s8>), [[COPY3]]
273-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<8 x s8>) = G_AND [[ICMP]], [[ICMP1]]
274-
; CHECK-NEXT: $d0 = COPY [[AND]](<8 x s8>)
275-
; CHECK-NEXT: RET_ReallyLR implicit $d0
276-
%0:_(<8 x s8>) = COPY $d0
277-
%1:_(<8 x s8>) = COPY $d1
278-
%2:_(<8 x s8>) = COPY $d2
279-
%3:_(<8 x s8>) = COPY $d3
280-
%4:_(<8 x s1>) = G_ICMP intpred(eq), %0(<8 x s8>), %1
281-
%5:_(<8 x s1>) = G_ICMP intpred(eq), %2(<8 x s8>), %3
282-
%6:_(<8 x s1>) = G_AND %4, %5
283-
%7:_(<8 x s8>) = G_ANYEXT %6
284-
$d0 = COPY %7:_(<8 x s8>)
285-
RET_ReallyLR implicit $d0
286-
...
287-
---
288-
name: and_v16s1
289-
tracksRegLiveness: true
290-
body: |
291-
bb.1:
292-
liveins: $q0, $q1, $q2, $q3
293-
294-
; CHECK-LABEL: name: and_v16s1
295-
; CHECK: liveins: $q0, $q1, $q2, $q3
296-
; CHECK-NEXT: {{ $}}
297-
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
298-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
299-
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY $q2
300-
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<16 x s8>) = COPY $q3
301-
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY]](<16 x s8>), [[COPY1]]
302-
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY2]](<16 x s8>), [[COPY3]]
303-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<16 x s8>) = G_AND [[ICMP]], [[ICMP1]]
304-
; CHECK-NEXT: $q0 = COPY [[AND]](<16 x s8>)
305-
; CHECK-NEXT: RET_ReallyLR implicit $q0
306-
%0:_(<16 x s8>) = COPY $q0
307-
%1:_(<16 x s8>) = COPY $q1
308-
%2:_(<16 x s8>) = COPY $q2
309-
%3:_(<16 x s8>) = COPY $q3
310-
%4:_(<16 x s1>) = G_ICMP intpred(eq), %0(<16 x s8>), %1
311-
%5:_(<16 x s1>) = G_ICMP intpred(eq), %2(<16 x s8>), %3
312-
%6:_(<16 x s1>) = G_AND %4, %5
313-
%7:_(<16 x s8>) = G_ANYEXT %6
314-
$q0 = COPY %7:_(<16 x s8>)
315-
RET_ReallyLR implicit $q0
316-
...

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