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[NFC][RISCV] Pass file through update_llc_tests to fix whitespace issues
While addressing RVV frame layout issues I found this file had whitespace differences that made diffs noisier than they should be. Differential Revision: https://reviews.llvm.org/D98800
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‎llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll

Lines changed: 89 additions & 88 deletions
Original file line numberDiff line numberDiff line change
@@ -1,39 +1,40 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
12
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+m -verify-machineinstrs < %s | FileCheck %s
23

34
define void @rvv_vla(i64 %n, i64 %i) nounwind {
45
; CHECK-LABEL: rvv_vla:
56
; CHECK: # %bb.0:
6-
; CHECK-NEXT: addi sp, sp, -32
7-
; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
8-
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
9-
; CHECK-NEXT: addi s0, sp, 32
10-
; CHECK-NEXT: csrr a2, vlenb
11-
; CHECK-NEXT: addi a3, zero, 3
12-
; CHECK-NEXT: mul a2, a2, a3
13-
; CHECK-NEXT: sub sp, sp, a2
14-
; CHECK-NEXT: slli a0, a0, 2
15-
; CHECK-NEXT: addi a0, a0, 15
16-
; CHECK-NEXT: andi a0, a0, -16
17-
; CHECK-NEXT: sub a0, sp, a0
18-
; CHECK-NEXT: mv sp, a0
19-
; CHECK-NEXT: csrr a2, vlenb
20-
; CHECK-NEXT: sub a2, s0, a2
21-
; CHECK-NEXT: addi a2, a2, -32
22-
; CHECK-NEXT: vl1re64.v v25, (a2)
23-
; CHECK-NEXT: csrr a2, vlenb
24-
; CHECK-NEXT: addi a3, zero, 3
25-
; CHECK-NEXT: mul a2, a2, a3
26-
; CHECK-NEXT: sub a2, s0, a2
27-
; CHECK-NEXT: addi a2, a2, -32
28-
; CHECK-NEXT: vl2re64.v v26, (a2)
29-
; CHECK-NEXT: slli a1, a1, 2
30-
; CHECK-NEXT: add a0, a0, a1
31-
; CHECK-NEXT: lw a0, 0(a0)
32-
; CHECK-NEXT: addi sp, s0, -32
33-
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
34-
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
35-
; CHECK-NEXT: addi sp, sp, 32
36-
; CHECK-NEXT: ret
7+
; CHECK-NEXT: addi sp, sp, -32
8+
; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
9+
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
10+
; CHECK-NEXT: addi s0, sp, 32
11+
; CHECK-NEXT: csrr a2, vlenb
12+
; CHECK-NEXT: addi a3, zero, 3
13+
; CHECK-NEXT: mul a2, a2, a3
14+
; CHECK-NEXT: sub sp, sp, a2
15+
; CHECK-NEXT: slli a0, a0, 2
16+
; CHECK-NEXT: addi a0, a0, 15
17+
; CHECK-NEXT: andi a0, a0, -16
18+
; CHECK-NEXT: sub a0, sp, a0
19+
; CHECK-NEXT: mv sp, a0
20+
; CHECK-NEXT: csrr a2, vlenb
21+
; CHECK-NEXT: sub a2, s0, a2
22+
; CHECK-NEXT: addi a2, a2, -32
23+
; CHECK-NEXT: vl1re64.v v25, (a2)
24+
; CHECK-NEXT: csrr a2, vlenb
25+
; CHECK-NEXT: addi a3, zero, 3
26+
; CHECK-NEXT: mul a2, a2, a3
27+
; CHECK-NEXT: sub a2, s0, a2
28+
; CHECK-NEXT: addi a2, a2, -32
29+
; CHECK-NEXT: vl2re64.v v26, (a2)
30+
; CHECK-NEXT: slli a1, a1, 2
31+
; CHECK-NEXT: add a0, a0, a1
32+
; CHECK-NEXT: lw a0, 0(a0)
33+
; CHECK-NEXT: addi sp, s0, -32
34+
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
35+
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
36+
; CHECK-NEXT: addi sp, sp, 32
37+
; CHECK-NEXT: ret
3738
%vla.addr = alloca i32, i64 %n
3839

3940
%v1.addr = alloca <vscale x 1 x i64>
@@ -50,28 +51,28 @@ define void @rvv_vla(i64 %n, i64 %i) nounwind {
5051
define void @rvv_overaligned() nounwind {
5152
; CHECK-LABEL: rvv_overaligned:
5253
; CHECK: # %bb.0:
53-
; CHECK-NEXT: addi sp, sp, -128
54-
; CHECK-NEXT: sd ra, 120(sp) # 8-byte Folded Spill
55-
; CHECK-NEXT: sd s0, 112(sp) # 8-byte Folded Spill
56-
; CHECK-NEXT: addi s0, sp, 128
57-
; CHECK-NEXT: csrr a0, vlenb
58-
; CHECK-NEXT: addi a1, zero, 3
59-
; CHECK-NEXT: mul a0, a0, a1
60-
; CHECK-NEXT: sub sp, sp, a0
61-
; CHECK-NEXT: andi sp, sp, -64
62-
; CHECK-NEXT: csrr a0, vlenb
63-
; CHECK-NEXT: slli a0, a0, 1
64-
; CHECK-NEXT: add a0, sp, a0
65-
; CHECK-NEXT: addi a0, a0, 112
66-
; CHECK-NEXT: vl1re64.v v25, (a0)
67-
; CHECK-NEXT: addi a0, sp, 112
68-
; CHECK-NEXT: vl2re64.v v26, (a0)
69-
; CHECK-NEXT: lw a0, 64(sp)
70-
; CHECK-NEXT: addi sp, s0, -128
71-
; CHECK-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
72-
; CHECK-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
73-
; CHECK-NEXT: addi sp, sp, 128
74-
; CHECK-NEXT: ret
54+
; CHECK-NEXT: addi sp, sp, -128
55+
; CHECK-NEXT: sd ra, 120(sp) # 8-byte Folded Spill
56+
; CHECK-NEXT: sd s0, 112(sp) # 8-byte Folded Spill
57+
; CHECK-NEXT: addi s0, sp, 128
58+
; CHECK-NEXT: csrr a0, vlenb
59+
; CHECK-NEXT: addi a1, zero, 3
60+
; CHECK-NEXT: mul a0, a0, a1
61+
; CHECK-NEXT: sub sp, sp, a0
62+
; CHECK-NEXT: andi sp, sp, -64
63+
; CHECK-NEXT: csrr a0, vlenb
64+
; CHECK-NEXT: slli a0, a0, 1
65+
; CHECK-NEXT: add a0, sp, a0
66+
; CHECK-NEXT: addi a0, a0, 112
67+
; CHECK-NEXT: vl1re64.v v25, (a0)
68+
; CHECK-NEXT: addi a0, sp, 112
69+
; CHECK-NEXT: vl2re64.v v26, (a0)
70+
; CHECK-NEXT: lw a0, 64(sp)
71+
; CHECK-NEXT: addi sp, s0, -128
72+
; CHECK-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
73+
; CHECK-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
74+
; CHECK-NEXT: addi sp, sp, 128
75+
; CHECK-NEXT: ret
7576
%overaligned = alloca i32, align 64
7677

7778
%v1.addr = alloca <vscale x 1 x i64>
@@ -85,41 +86,41 @@ define void @rvv_overaligned() nounwind {
8586
}
8687

8788
define void @rvv_vla_and_overaligned(i64 %n, i64 %i) nounwind {
88-
; CHECK-LABEL: rvv_vla_and_overaligned
89+
; CHECK-LABEL: rvv_vla_and_overaligned:
8990
; CHECK: # %bb.0:
90-
; CHECK-NEXT: addi sp, sp, -128
91-
; CHECK-NEXT: sd ra, 120(sp) # 8-byte Folded Spill
92-
; CHECK-NEXT: sd s0, 112(sp) # 8-byte Folded Spill
93-
; CHECK-NEXT: sd s1, 104(sp) # 8-byte Folded Spill
94-
; CHECK-NEXT: addi s0, sp, 128
95-
; CHECK-NEXT: csrr a2, vlenb
96-
; CHECK-NEXT: addi a3, zero, 3
97-
; CHECK-NEXT: mul a2, a2, a3
98-
; CHECK-NEXT: sub sp, sp, a2
99-
; CHECK-NEXT: andi sp, sp, -64
100-
; CHECK-NEXT: mv s1, sp
101-
; CHECK-NEXT: slli a0, a0, 2
102-
; CHECK-NEXT: addi a0, a0, 15
103-
; CHECK-NEXT: andi a0, a0, -16
104-
; CHECK-NEXT: sub a0, sp, a0
105-
; CHECK-NEXT: mv sp, a0
106-
; CHECK-NEXT: csrr a2, vlenb
107-
; CHECK-NEXT: slli a2, a2, 1
108-
; CHECK-NEXT: add a2, s1, a2
109-
; CHECK-NEXT: addi a2, a2, 96
110-
; CHECK-NEXT: vl1re64.v v25, (a2)
111-
; CHECK-NEXT: addi a2, s1, 96
112-
; CHECK-NEXT: vl2re64.v v26, (a2)
113-
; CHECK-NEXT: lw a2, 64(s1)
114-
; CHECK-NEXT: slli a1, a1, 2
115-
; CHECK-NEXT: add a0, a0, a1
116-
; CHECK-NEXT: lw a0, 0(a0)
117-
; CHECK-NEXT: addi sp, s0, -128
118-
; CHECK-NEXT: ld s1, 104(sp) # 8-byte Folded Reload
119-
; CHECK-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
120-
; CHECK-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
121-
; CHECK-NEXT: addi sp, sp, 128
122-
; CHECK-NEXT: ret
91+
; CHECK-NEXT: addi sp, sp, -128
92+
; CHECK-NEXT: sd ra, 120(sp) # 8-byte Folded Spill
93+
; CHECK-NEXT: sd s0, 112(sp) # 8-byte Folded Spill
94+
; CHECK-NEXT: sd s1, 104(sp) # 8-byte Folded Spill
95+
; CHECK-NEXT: addi s0, sp, 128
96+
; CHECK-NEXT: csrr a2, vlenb
97+
; CHECK-NEXT: addi a3, zero, 3
98+
; CHECK-NEXT: mul a2, a2, a3
99+
; CHECK-NEXT: sub sp, sp, a2
100+
; CHECK-NEXT: andi sp, sp, -64
101+
; CHECK-NEXT: mv s1, sp
102+
; CHECK-NEXT: slli a0, a0, 2
103+
; CHECK-NEXT: addi a0, a0, 15
104+
; CHECK-NEXT: andi a0, a0, -16
105+
; CHECK-NEXT: sub a0, sp, a0
106+
; CHECK-NEXT: mv sp, a0
107+
; CHECK-NEXT: csrr a2, vlenb
108+
; CHECK-NEXT: slli a2, a2, 1
109+
; CHECK-NEXT: add a2, s1, a2
110+
; CHECK-NEXT: addi a2, a2, 96
111+
; CHECK-NEXT: vl1re64.v v25, (a2)
112+
; CHECK-NEXT: addi a2, s1, 96
113+
; CHECK-NEXT: vl2re64.v v26, (a2)
114+
; CHECK-NEXT: lw a2, 64(s1)
115+
; CHECK-NEXT: slli a1, a1, 2
116+
; CHECK-NEXT: add a0, a0, a1
117+
; CHECK-NEXT: lw a0, 0(a0)
118+
; CHECK-NEXT: addi sp, s0, -128
119+
; CHECK-NEXT: ld s1, 104(sp) # 8-byte Folded Reload
120+
; CHECK-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
121+
; CHECK-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
122+
; CHECK-NEXT: addi sp, sp, 128
123+
; CHECK-NEXT: ret
123124
%overaligned = alloca i32, align 64
124125
%vla.addr = alloca i32, i64 %n
125126

@@ -134,4 +135,4 @@ define void @rvv_vla_and_overaligned(i64 %n, i64 %i) nounwind {
134135
%s2 = load volatile i32, i32* %p
135136
ret void
136137

137-
}
138+
}

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