@@ -140,11 +140,6 @@ class PPCInstrInfo : public PPCGenInstrInfo {
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unsigned &OpNoForForwarding,
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bool &SeenIntermediateUse) const ;
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- // In PostRA phase, try to find instruction defines \p Reg before \p MI.
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- // \p SeenIntermediate is set to true if uses between DefMI and \p MI exist.
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- MachineInstr *getDefMIPostRA (unsigned Reg, MachineInstr &MI,
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- bool &SeenIntermediateUse) const ;
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-
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// Can the user MI have it's source at index \p OpNoForForwarding
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// forwarded from an add-immediate that feeds it?
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bool isUseMIElgibleForForwarding (MachineInstr &MI, const ImmInstrInfo &III,
@@ -447,6 +442,11 @@ class PPCInstrInfo : public PPCGenInstrInfo {
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bool instrHasImmForm (unsigned Opc, bool IsVFReg, ImmInstrInfo &III,
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bool PostRA) const ;
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+ // In PostRA phase, try to find instruction defines \p Reg before \p MI.
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+ // \p SeenIntermediate is set to true if uses between DefMI and \p MI exist.
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+ MachineInstr *getDefMIPostRA (unsigned Reg, MachineInstr &MI,
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+ bool &SeenIntermediateUse) const ;
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+
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// / getRegNumForOperand - some operands use different numbering schemes
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// / for the same registers. For example, a VSX instruction may have any of
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// / vs0-vs63 allocated whereas an Altivec instruction could only have
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