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[RISCV] Rename vfredusum/vfredosum intrinsic test files. Merge some tests. NFC
I recently renamed some tests from vfredsum to vfredusum without noticing they tested both ordered and unordered reductions. This patch renames them back. I've also merged test files for vfwredosum/vfwredusum into a single file for consistency with the other 3 floating point reduction test files. The inconsistency is what caused my original confusion.
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-225
lines changed

5 files changed

+218
-225
lines changed

‎clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredusum.c renamed to ‎clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c

File renamed without changes.

‎clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredusum.c renamed to ‎clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c

File renamed without changes.

‎clang/test/CodeGen/RISCV/rvv-intrinsics/vfredusum.c renamed to ‎clang/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c

File renamed without changes.

‎clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredosum.c renamed to ‎clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c

Lines changed: 218 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -223,3 +223,221 @@ vfloat32m1_t test_vfwredosum_vs_f16m4_f32m1_m (vbool4_t mask, vfloat32m1_t dest,
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vfloat32m1_t test_vfwredosum_vs_f16m8_f32m1_m (vbool2_t mask, vfloat32m1_t dest, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
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return vfwredosum_vs_f16m8_f32m1_m(mask, dest, vector, scalar, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32mf2_f64m1(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
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//
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vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1(vfloat64m1_t dst,
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vfloat32mf2_t vector,
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vfloat64m1_t scalar, size_t vl) {
235+
return vfwredusum_vs_f32mf2_f64m1(dst, vector, scalar, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m1_f64m1(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
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//
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vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1(vfloat64m1_t dst,
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vfloat32m1_t vector,
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vfloat64m1_t scalar, size_t vl) {
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return vfwredusum_vs_f32m1_f64m1(dst, vector, scalar, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m2_f64m1(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
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//
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vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1(vfloat64m1_t dst,
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vfloat32m2_t vector,
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vfloat64m1_t scalar, size_t vl) {
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return vfwredusum_vs_f32m2_f64m1(dst, vector, scalar, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m4_f64m1(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
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//
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vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1(vfloat64m1_t dst,
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vfloat32m4_t vector,
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vfloat64m1_t scalar, size_t vl) {
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return vfwredusum_vs_f32m4_f64m1(dst, vector, scalar, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m8_f64m1(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
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//
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vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1(vfloat64m1_t dst,
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vfloat32m8_t vector,
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vfloat64m1_t scalar, size_t vl) {
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return vfwredusum_vs_f32m8_f64m1(dst, vector, scalar, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32mf2_f64m1_m(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
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//
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vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_m(vbool64_t mask, vfloat64m1_t dst,
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vfloat32mf2_t vector,
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vfloat64m1_t scalar, size_t vl) {
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return vfwredusum_vs_f32mf2_f64m1_m(mask, dst, vector, scalar, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m1_f64m1_m(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
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//
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vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1_m(vbool32_t mask, vfloat64m1_t dst,
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vfloat32m1_t vector,
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vfloat64m1_t scalar, size_t vl) {
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return vfwredusum_vs_f32m1_f64m1_m(mask, dst, vector, scalar, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m2_f64m1_m(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
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//
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vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1_m(vbool16_t mask, vfloat64m1_t dst,
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vfloat32m2_t vector,
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vfloat64m1_t scalar, size_t vl) {
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return vfwredusum_vs_f32m2_f64m1_m(mask, dst, vector, scalar, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m4_f64m1_m(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
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//
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vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1_m(vbool8_t mask, vfloat64m1_t dst,
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vfloat32m4_t vector,
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vfloat64m1_t scalar, size_t vl) {
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return vfwredusum_vs_f32m4_f64m1_m(mask, dst, vector, scalar, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m8_f64m1_m(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
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//
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vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1_m(vbool4_t mask, vfloat64m1_t dst,
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vfloat32m8_t vector,
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vfloat64m1_t scalar, size_t vl) {
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return vfwredusum_vs_f32m8_f64m1_m(mask, dst, vector, scalar, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16mf4_f32m1(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
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//
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vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1 (vfloat32m1_t dest, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
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return vfwredusum_vs_f16mf4_f32m1(dest, vector, scalar, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16mf2_f32m1(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
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//
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vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1 (vfloat32m1_t dest, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
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return vfwredusum_vs_f16mf2_f32m1(dest, vector, scalar, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16m1_f32m1(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
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//
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vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1 (vfloat32m1_t dest, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
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return vfwredusum_vs_f16m1_f32m1(dest, vector, scalar, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16m2_f32m1(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
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//
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vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1 (vfloat32m1_t dest, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
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return vfwredusum_vs_f16m2_f32m1(dest, vector, scalar, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16m4_f32m1(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
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//
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vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1 (vfloat32m1_t dest, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
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return vfwredusum_vs_f16m4_f32m1(dest, vector, scalar, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16m8_f32m1(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
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//
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vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1 (vfloat32m1_t dest, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
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return vfwredusum_vs_f16m8_f32m1(dest, vector, scalar, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16mf4_f32m1_m(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
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//
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vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1_m (vbool64_t mask, vfloat32m1_t dest, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {
397+
return vfwredusum_vs_f16mf4_f32m1_m(mask, dest, vector, scalar, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16mf2_f32m1_m(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
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//
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vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1_m (vbool32_t mask, vfloat32m1_t dest, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) {
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return vfwredusum_vs_f16mf2_f32m1_m(mask, dest, vector, scalar, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16m1_f32m1_m(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
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//
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vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1_m (vbool16_t mask, vfloat32m1_t dest, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) {
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return vfwredusum_vs_f16m1_f32m1_m(mask, dest, vector, scalar, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16m2_f32m1_m(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
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//
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vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1_m (vbool8_t mask, vfloat32m1_t dest, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) {
424+
return vfwredusum_vs_f16m2_f32m1_m(mask, dest, vector, scalar, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16m4_f32m1_m(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
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//
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vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1_m (vbool4_t mask, vfloat32m1_t dest, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) {
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return vfwredusum_vs_f16m4_f32m1_m(mask, dest, vector, scalar, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16m8_f32m1_m(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
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//
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vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1_m (vbool2_t mask, vfloat32m1_t dest, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
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return vfwredusum_vs_f16m8_f32m1_m(mask, dest, vector, scalar, vl);
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}

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