[Hexagon] Add machine verification to some tests

jayfoad · jayfoad · commit 9951d437d30e · 2021-11-02T15:41:30.000Z
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-concat-vectors-bool.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-concat-vectors-bool.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon < %s | FileCheck %s
+; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s
 
 ; Check for successful compilation.
 ; CHECK: sfcmp
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-const-splat-bitcast.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-const-splat-bitcast.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon < %s | FileCheck %s
+; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s
 
 ; The generation of a constant vector in the selection step resulted in
 ; a VSPLAT, which, deeper in the expression tree had an unrelated BITCAST.
diff --git a/llvm/test/CodeGen/Hexagon/bit-extract-off.ll b/llvm/test/CodeGen/Hexagon/bit-extract-off.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon < %s | FileCheck %s
+; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s
 ; CHECK: extractu(r1,#31,#0)
 
 ; In the IR this was an extract of 31 bits starting at position 32 in r1:0.

Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-; RUN: llc -march=hexagon < %s \| FileCheck %s`
	`1`	`+; RUN: llc -march=hexagon -verify-machineinstrs < %s \| FileCheck %s`
`2`	`2`
`3`	`3`	`; Check for successful compilation.`
`4`	`4`	`; CHECK: sfcmp`