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[SelectionDAG][RISCV] Add tests showing missed scalable-splat optimizations
These tests show missed opportunities in the SelectionDAG layer when dealing with scalable-vector splats. All of these are handled for the equivalent `ISD::BUILD_VECTOR` code, and the tests have largely been translated from the equivalent X86 tests. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D106574
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‎llvm/test/CodeGen/RISCV/rvv/combine-splats.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v < %s | FileCheck %s
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; fold (and (or x, C), D) -> D if (C & D) == D
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define <vscale x 4 x i32> @and_or_nxv4i32(<vscale x 4 x i32> %A) {
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; CHECK-LABEL: and_or_nxv4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi a0, zero, 255
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; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
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; CHECK-NEXT: vor.vx v26, v8, a0
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; CHECK-NEXT: vand.vi v8, v26, 8
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; CHECK-NEXT: ret
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%ins1 = insertelement <vscale x 4 x i32> poison, i32 255, i32 0
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%splat1 = shufflevector <vscale x 4 x i32> %ins1, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
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%ins2 = insertelement <vscale x 4 x i32> poison, i32 8, i32 0
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%splat2 = shufflevector <vscale x 4 x i32> %ins2, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
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%v1 = or <vscale x 4 x i32> %A, %splat1
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%v2 = and <vscale x 4 x i32> %v1, %splat2
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ret <vscale x 4 x i32> %v2
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}
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; (or (and X, c1), c2) -> (and (or X, c2), c1|c2) iff (c1 & c2) != 0
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define <vscale x 2 x i64> @or_and_nxv2i64(<vscale x 2 x i64> %a0) {
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; CHECK-LABEL: or_and_nxv2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
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; CHECK-NEXT: vand.vi v26, v8, 7
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; CHECK-NEXT: vor.vi v8, v26, 3
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; CHECK-NEXT: ret
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%ins1 = insertelement <vscale x 2 x i64> poison, i64 7, i32 0
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%splat1 = shufflevector <vscale x 2 x i64> %ins1, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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%ins2 = insertelement <vscale x 2 x i64> poison, i64 3, i32 0
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%splat2 = shufflevector <vscale x 2 x i64> %ins2, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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%v1 = and <vscale x 2 x i64> %a0, %splat1
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%v2 = or <vscale x 2 x i64> %v1, %splat2
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ret <vscale x 2 x i64> %v2
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}
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; If all masked bits are going to be set, that's a constant fold.
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define <vscale x 2 x i64> @or_and_nxv2i64_fold(<vscale x 2 x i64> %a0) {
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; CHECK-LABEL: or_and_nxv2i64_fold:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
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; CHECK-NEXT: vand.vi v26, v8, 1
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; CHECK-NEXT: vor.vi v8, v26, 3
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; CHECK-NEXT: ret
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%ins1 = insertelement <vscale x 2 x i64> poison, i64 1, i32 0
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%splat1 = shufflevector <vscale x 2 x i64> %ins1, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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%ins2 = insertelement <vscale x 2 x i64> poison, i64 3, i32 0
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%splat2 = shufflevector <vscale x 2 x i64> %ins2, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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%v1 = and <vscale x 2 x i64> %a0, %splat1
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%v2 = or <vscale x 2 x i64> %v1, %splat2
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ret <vscale x 2 x i64> %v2
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}
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; fold (shl (shl x, c1), c2) -> (shl x, (add c1, c2))
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define <vscale x 4 x i32> @combine_vec_shl_shl(<vscale x 4 x i32> %x) {
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; CHECK-LABEL: combine_vec_shl_shl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi a0, zero, 2
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; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
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; CHECK-NEXT: vmv.s.x v26, a0
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; CHECK-NEXT: addi a0, zero, 4
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; CHECK-NEXT: vmv.s.x v28, a0
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; CHECK-NEXT: vsll.vv v26, v8, v26
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; CHECK-NEXT: vsll.vv v8, v26, v28
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; CHECK-NEXT: ret
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%ins1 = insertelement <vscale x 4 x i32> poison, i32 2, i32 0
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%splat1 = shufflevector <vscale x 4 x i32> %ins1, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
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%ins2 = insertelement <vscale x 4 x i32> poison, i32 4, i32 0
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%splat2 = shufflevector <vscale x 4 x i32> %ins2, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
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%v1 = shl <vscale x 4 x i32> %x, %ins1
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%v2 = shl <vscale x 4 x i32> %v1, %ins2
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ret <vscale x 4 x i32> %v2
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}
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; fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
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define <vscale x 2 x i32> @combine_vec_ashr_ashr(<vscale x 2 x i32> %x) {
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; CHECK-LABEL: combine_vec_ashr_ashr:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
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; CHECK-NEXT: vsra.vi v25, v8, 2
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; CHECK-NEXT: vsra.vi v8, v25, 4
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; CHECK-NEXT: ret
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%ins1 = insertelement <vscale x 2 x i32> poison, i32 2, i32 0
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%splat1 = shufflevector <vscale x 2 x i32> %ins1, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
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%ins2 = insertelement <vscale x 2 x i32> poison, i32 4, i32 0
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%splat2 = shufflevector <vscale x 2 x i32> %ins2, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
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%v1 = ashr <vscale x 2 x i32> %x, %splat1
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%v2 = ashr <vscale x 2 x i32> %v1, %splat2
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ret <vscale x 2 x i32> %v2
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}
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; fold (srl (srl x, c1), c2) -> (srl x, (add c1, c2))
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define <vscale x 8 x i16> @combine_vec_lshr_lshr(<vscale x 8 x i16> %x) {
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; CHECK-LABEL: combine_vec_lshr_lshr:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
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; CHECK-NEXT: vsrl.vi v26, v8, 4
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; CHECK-NEXT: vsrl.vi v8, v26, 4
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; CHECK-NEXT: ret
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%ins1 = insertelement <vscale x 8 x i16> poison, i16 2, i32 0
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%splat1 = shufflevector <vscale x 8 x i16> %ins1, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
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%ins2 = insertelement <vscale x 8 x i16> poison, i16 4, i32 0
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%splat2 = shufflevector <vscale x 8 x i16> %ins2, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
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%v1 = lshr <vscale x 8 x i16> %x, %splat2
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%v2 = lshr <vscale x 8 x i16> %v1, %splat2
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ret <vscale x 8 x i16> %v2
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}

‎llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v < %s | FileCheck %s --check-prefix=RV32
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; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v < %s | FileCheck %s --check-prefix=RV64
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define <vscale x 1 x i16> @test_urem_vec_even_divisor_eq0(<vscale x 1 x i16> %x) nounwind {
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; RV32-LABEL: test_urem_vec_even_divisor_eq0:
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; RV32: # %bb.0:
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; RV32-NEXT: lui a0, 1048571
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; RV32-NEXT: addi a0, a0, -1365
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; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
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; RV32-NEXT: vmulhu.vx v25, v8, a0
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; RV32-NEXT: vsrl.vi v25, v25, 2
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; RV32-NEXT: addi a0, zero, 6
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; RV32-NEXT: vnmsub.vx v25, a0, v8
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; RV32-NEXT: vmv.v.i v26, 0
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; RV32-NEXT: vmsne.vi v0, v25, 0
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; RV32-NEXT: vmerge.vim v8, v26, -1, v0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_urem_vec_even_divisor_eq0:
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; RV64: # %bb.0:
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; RV64-NEXT: lui a0, 1048571
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; RV64-NEXT: addiw a0, a0, -1365
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; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
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; RV64-NEXT: vmulhu.vx v25, v8, a0
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; RV64-NEXT: vsrl.vi v25, v25, 2
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; RV64-NEXT: addi a0, zero, 6
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; RV64-NEXT: vnmsub.vx v25, a0, v8
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; RV64-NEXT: vmv.v.i v26, 0
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; RV64-NEXT: vmsne.vi v0, v25, 0
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; RV64-NEXT: vmerge.vim v8, v26, -1, v0
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; RV64-NEXT: ret
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%ins1 = insertelement <vscale x 1 x i16> poison, i16 6, i32 0
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%splat1 = shufflevector <vscale x 1 x i16> %ins1, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
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%urem = urem <vscale x 1 x i16> %x, %splat1
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%ins2 = insertelement <vscale x 1 x i16> poison, i16 0, i32 0
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%splat2 = shufflevector <vscale x 1 x i16> %ins2, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
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%cmp = icmp ne <vscale x 1 x i16> %urem, %splat2
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%ext = sext <vscale x 1 x i1> %cmp to <vscale x 1 x i16>
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ret <vscale x 1 x i16> %ext
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}
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define <vscale x 1 x i16> @test_urem_vec_odd_divisor_eq0(<vscale x 1 x i16> %x) nounwind {
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; RV32-LABEL: test_urem_vec_odd_divisor_eq0:
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; RV32: # %bb.0:
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; RV32-NEXT: lui a0, 1048573
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; RV32-NEXT: addi a0, a0, -819
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; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
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; RV32-NEXT: vmulhu.vx v25, v8, a0
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; RV32-NEXT: vsrl.vi v25, v25, 2
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; RV32-NEXT: addi a0, zero, 5
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; RV32-NEXT: vnmsub.vx v25, a0, v8
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; RV32-NEXT: vmv.v.i v26, 0
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; RV32-NEXT: vmsne.vi v0, v25, 0
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; RV32-NEXT: vmerge.vim v8, v26, -1, v0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_urem_vec_odd_divisor_eq0:
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; RV64: # %bb.0:
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; RV64-NEXT: lui a0, 1048573
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; RV64-NEXT: addiw a0, a0, -819
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; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
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; RV64-NEXT: vmulhu.vx v25, v8, a0
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; RV64-NEXT: vsrl.vi v25, v25, 2
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; RV64-NEXT: addi a0, zero, 5
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; RV64-NEXT: vnmsub.vx v25, a0, v8
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; RV64-NEXT: vmv.v.i v26, 0
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; RV64-NEXT: vmsne.vi v0, v25, 0
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; RV64-NEXT: vmerge.vim v8, v26, -1, v0
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; RV64-NEXT: ret
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%ins1 = insertelement <vscale x 1 x i16> poison, i16 5, i32 0
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%splat1 = shufflevector <vscale x 1 x i16> %ins1, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
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%urem = urem <vscale x 1 x i16> %x, %splat1
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%ins2 = insertelement <vscale x 1 x i16> poison, i16 0, i32 0
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%splat2 = shufflevector <vscale x 1 x i16> %ins2, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
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%cmp = icmp ne <vscale x 1 x i16> %urem, %splat2
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%ext = sext <vscale x 1 x i1> %cmp to <vscale x 1 x i16>
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ret <vscale x 1 x i16> %ext
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}
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define <vscale x 1 x i16> @test_urem_vec_even_divisor_eq1(<vscale x 1 x i16> %x) nounwind {
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; RV32-LABEL: test_urem_vec_even_divisor_eq1:
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; RV32: # %bb.0:
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; RV32-NEXT: lui a0, 1048571
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; RV32-NEXT: addi a0, a0, -1365
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; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
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; RV32-NEXT: vmulhu.vx v25, v8, a0
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; RV32-NEXT: vsrl.vi v25, v25, 2
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; RV32-NEXT: addi a0, zero, 6
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; RV32-NEXT: vnmsub.vx v25, a0, v8
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; RV32-NEXT: vmsne.vi v0, v25, 1
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; RV32-NEXT: vmv.v.i v25, 0
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; RV32-NEXT: vmerge.vim v8, v25, -1, v0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_urem_vec_even_divisor_eq1:
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; RV64: # %bb.0:
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; RV64-NEXT: lui a0, 1048571
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; RV64-NEXT: addiw a0, a0, -1365
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; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
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; RV64-NEXT: vmulhu.vx v25, v8, a0
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; RV64-NEXT: vsrl.vi v25, v25, 2
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; RV64-NEXT: addi a0, zero, 6
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; RV64-NEXT: vnmsub.vx v25, a0, v8
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; RV64-NEXT: vmsne.vi v0, v25, 1
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; RV64-NEXT: vmv.v.i v25, 0
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; RV64-NEXT: vmerge.vim v8, v25, -1, v0
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; RV64-NEXT: ret
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%ins1 = insertelement <vscale x 1 x i16> poison, i16 6, i32 0
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%splat1 = shufflevector <vscale x 1 x i16> %ins1, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
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%urem = urem <vscale x 1 x i16> %x, %splat1
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%ins2 = insertelement <vscale x 1 x i16> poison, i16 1, i32 0
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%splat2 = shufflevector <vscale x 1 x i16> %ins2, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
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%cmp = icmp ne <vscale x 1 x i16> %urem, %splat2
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%ext = sext <vscale x 1 x i1> %cmp to <vscale x 1 x i16>
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ret <vscale x 1 x i16> %ext
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}
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define <vscale x 1 x i16> @test_urem_vec_odd_divisor_eq1(<vscale x 1 x i16> %x) nounwind {
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; RV32-LABEL: test_urem_vec_odd_divisor_eq1:
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; RV32: # %bb.0:
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; RV32-NEXT: lui a0, 1048573
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; RV32-NEXT: addi a0, a0, -819
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; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
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; RV32-NEXT: vmulhu.vx v25, v8, a0
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; RV32-NEXT: vsrl.vi v25, v25, 2
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; RV32-NEXT: addi a0, zero, 5
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; RV32-NEXT: vnmsub.vx v25, a0, v8
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; RV32-NEXT: vmsne.vi v0, v25, 1
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; RV32-NEXT: vmv.v.i v25, 0
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; RV32-NEXT: vmerge.vim v8, v25, -1, v0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test_urem_vec_odd_divisor_eq1:
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; RV64: # %bb.0:
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; RV64-NEXT: lui a0, 1048573
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; RV64-NEXT: addiw a0, a0, -819
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; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, mu
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; RV64-NEXT: vmulhu.vx v25, v8, a0
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; RV64-NEXT: vsrl.vi v25, v25, 2
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; RV64-NEXT: addi a0, zero, 5
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; RV64-NEXT: vnmsub.vx v25, a0, v8
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; RV64-NEXT: vmsne.vi v0, v25, 1
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; RV64-NEXT: vmv.v.i v25, 0
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; RV64-NEXT: vmerge.vim v8, v25, -1, v0
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; RV64-NEXT: ret
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%ins1 = insertelement <vscale x 1 x i16> poison, i16 5, i32 0
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%splat1 = shufflevector <vscale x 1 x i16> %ins1, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
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%urem = urem <vscale x 1 x i16> %x, %splat1
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%ins2 = insertelement <vscale x 1 x i16> poison, i16 1, i32 0
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%splat2 = shufflevector <vscale x 1 x i16> %ins2, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
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%cmp = icmp ne <vscale x 1 x i16> %urem, %splat2
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%ext = sext <vscale x 1 x i1> %cmp to <vscale x 1 x i16>
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ret <vscale x 1 x i16> %ext
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}

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