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Revert "[CodeGen][SVE] Calculate correct type legalization for scalable vectors."
Seems to break some buildbots, reverting the patch for now. This reverts commit 164f4b9.
1 parent 28c2bdf commit 9bcef27

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8 files changed

+24
-115
lines changed

8 files changed

+24
-115
lines changed

llvm/include/llvm/CodeGen/TargetLowering.h

Lines changed: 1 addition & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -210,13 +210,6 @@ class TargetLoweringBase {
210210
TypeWidenVector, // This vector should be widened into a larger vector.
211211
TypePromoteFloat, // Replace this float with a larger one.
212212
TypeSoftPromoteHalf, // Soften half to i16 and use float to do arithmetic.
213-
TypeScalarizeScalableVector, // This action is explicitly left unimplemented.
214-
// While it is theoretically possible to
215-
// legalize operations on scalable types with a
216-
// loop that handles the vscale * #lanes of the
217-
// vector, this is non-trivial at SelectionDAG
218-
// level and these types are better to be
219-
// widened or promoted.
220213
};
221214

222215
/// LegalizeKind holds the legalization kind that needs to happen to EVT
@@ -419,7 +412,7 @@ class TargetLoweringBase {
419412
virtual TargetLoweringBase::LegalizeTypeAction
420413
getPreferredVectorAction(MVT VT) const {
421414
// The default action for one element vectors is to scalarize
422-
if (VT.getVectorElementCount() == 1)
415+
if (VT.getVectorNumElements() == 1)
423416
return TypeScalarizeVector;
424417
// The default action for an odd-width vector is to widen.
425418
if (!VT.isPow2VectorType())

llvm/include/llvm/Support/TypeSize.h

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,6 @@
1515
#ifndef LLVM_SUPPORT_TYPESIZE_H
1616
#define LLVM_SUPPORT_TYPESIZE_H
1717

18-
#include "llvm/Support/MathExtras.h"
1918
#include "llvm/Support/WithColor.h"
2019

2120
#include <cstdint>
@@ -50,12 +49,6 @@ class ElementCount {
5049
bool operator!=(const ElementCount& RHS) const {
5150
return !(*this == RHS);
5251
}
53-
bool operator==(unsigned RHS) const { return Min == RHS && !Scalable; }
54-
bool operator!=(unsigned RHS) const { return !(*this == RHS); }
55-
56-
ElementCount NextPowerOf2() const {
57-
return ElementCount(llvm::NextPowerOf2(Min), Scalable);
58-
}
5952
};
6053

6154
// This class is used to represent the size of types. If the type is of fixed

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -344,8 +344,6 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
344344
return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
345345
BitConvertToInteger(GetScalarizedVector(InOp)));
346346
break;
347-
case TargetLowering::TypeScalarizeScalableVector:
348-
report_fatal_error("Scalarization of scalable vectors is not supported.");
349347
case TargetLowering::TypeSplitVector: {
350348
if (!NOutVT.isVector()) {
351349
// For example, i32 = BITCAST v2i16 on alpha. Convert the split

llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -245,9 +245,6 @@ bool DAGTypeLegalizer::run() {
245245
case TargetLowering::TypeLegal:
246246
LLVM_DEBUG(dbgs() << "Legal result type\n");
247247
break;
248-
case TargetLowering::TypeScalarizeScalableVector:
249-
report_fatal_error(
250-
"Scalarization of scalable vectors is not supported.");
251248
// The following calls must take care of *all* of the node's results,
252249
// not just the illegal result they were passed (this includes results
253250
// with a legal type). Results can be remapped using ReplaceValueWith,
@@ -310,9 +307,6 @@ bool DAGTypeLegalizer::run() {
310307
case TargetLowering::TypeLegal:
311308
LLVM_DEBUG(dbgs() << "Legal operand\n");
312309
continue;
313-
case TargetLowering::TypeScalarizeScalableVector:
314-
report_fatal_error(
315-
"Scalarization of scalable vectors is not supported.");
316310
// The following calls must either replace all of the node's results
317311
// using ReplaceValueWith, and return "false"; or update the node's
318312
// operands in place, and return "true".

llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -83,8 +83,6 @@ void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) {
8383
Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
8484
Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
8585
return;
86-
case TargetLowering::TypeScalarizeScalableVector:
87-
report_fatal_error("Scalarization of scalable vectors is not supported.");
8886
case TargetLowering::TypeWidenVector: {
8987
assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BITCAST");
9088
InOp = GetWidenedVector(InOp);

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1063,8 +1063,6 @@ void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
10631063
Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
10641064
Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
10651065
return;
1066-
case TargetLowering::TypeScalarizeScalableVector:
1067-
report_fatal_error("Scalarization of scalable vectors is not supported.");
10681066
}
10691067

10701068
// In the general case, convert the input to an integer and split it by hand.
@@ -3467,8 +3465,6 @@ SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
34673465
switch (getTypeAction(InVT)) {
34683466
case TargetLowering::TypeLegal:
34693467
break;
3470-
case TargetLowering::TypeScalarizeScalableVector:
3471-
report_fatal_error("Scalarization of scalable vectors is not supported.");
34723468
case TargetLowering::TypePromoteInteger: {
34733469
// If the incoming type is a vector that is being promoted, then
34743470
// we know that the elements are arranged differently and that we

llvm/lib/CodeGen/TargetLoweringBase.cpp

Lines changed: 17 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -823,7 +823,9 @@ TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
823823
"Promote may not follow Expand or Promote");
824824

825825
if (LA == TypeSplitVector)
826-
return LegalizeKind(LA, SVT.getHalfNumVectorElementsVT());
826+
return LegalizeKind(LA,
827+
EVT::getVectorVT(Context, SVT.getVectorElementType(),
828+
SVT.getVectorNumElements() / 2));
827829
if (LA == TypeScalarizeVector)
828830
return LegalizeKind(LA, SVT.getVectorElementType());
829831
return LegalizeKind(LA, NVT);
@@ -850,24 +852,21 @@ TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
850852
}
851853

852854
// Handle vector types.
853-
ElementCount NumElts = VT.getVectorElementCount();
855+
unsigned NumElts = VT.getVectorNumElements();
854856
EVT EltVT = VT.getVectorElementType();
855857

856858
// Vectors with only one element are always scalarized.
857859
if (NumElts == 1)
858860
return LegalizeKind(TypeScalarizeVector, EltVT);
859861

860-
if (VT.getVectorElementCount() == ElementCount(1, true))
861-
report_fatal_error("Cannot legalize this vector");
862-
863862
// Try to widen vector elements until the element type is a power of two and
864863
// promote it to a legal type later on, for example:
865864
// <3 x i8> -> <4 x i8> -> <4 x i32>
866865
if (EltVT.isInteger()) {
867866
// Vectors with a number of elements that is not a power of two are always
868867
// widened, for example <3 x i8> -> <4 x i8>.
869868
if (!VT.isPow2VectorType()) {
870-
NumElts = NumElts.NextPowerOf2();
869+
NumElts = (unsigned)NextPowerOf2(NumElts);
871870
EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
872871
return LegalizeKind(TypeWidenVector, NVT);
873872
}
@@ -916,7 +915,7 @@ TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
916915
// If there is no wider legal type, split the vector.
917916
while (true) {
918917
// Round up to the next power of 2.
919-
NumElts = NumElts.NextPowerOf2();
918+
NumElts = (unsigned)NextPowerOf2(NumElts);
920919

921920
// If there is no simple vector type with this many elements then there
922921
// cannot be a larger legal vector type. Note that this assumes that
@@ -939,7 +938,7 @@ TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
939938
}
940939

941940
// Vectors with illegal element types are expanded.
942-
EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorElementCount() / 2);
941+
EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
943942
return LegalizeKind(TypeSplitVector, NVT);
944943
}
945944

@@ -1258,7 +1257,7 @@ void TargetLoweringBase::computeRegisterProperties(
12581257
continue;
12591258

12601259
MVT EltVT = VT.getVectorElementType();
1261-
ElementCount EC = VT.getVectorElementCount();
1260+
unsigned NElts = VT.getVectorNumElements();
12621261
bool IsLegalWiderType = false;
12631262
bool IsScalable = VT.isScalableVector();
12641263
LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
@@ -1275,7 +1274,8 @@ void TargetLoweringBase::computeRegisterProperties(
12751274
// Promote vectors of integers to vectors with the same number
12761275
// of elements, with a wider element type.
12771276
if (SVT.getScalarSizeInBits() > EltVT.getSizeInBits() &&
1278-
SVT.getVectorElementCount() == EC && isTypeLegal(SVT)) {
1277+
SVT.getVectorNumElements() == NElts &&
1278+
SVT.isScalableVector() == IsScalable && isTypeLegal(SVT)) {
12791279
TransformToType[i] = SVT;
12801280
RegisterTypeForVT[i] = SVT;
12811281
NumRegistersForVT[i] = 1;
@@ -1290,13 +1290,13 @@ void TargetLoweringBase::computeRegisterProperties(
12901290
}
12911291

12921292
case TypeWidenVector:
1293-
if (isPowerOf2_32(EC.Min)) {
1293+
if (isPowerOf2_32(NElts)) {
12941294
// Try to widen the vector.
12951295
for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
12961296
MVT SVT = (MVT::SimpleValueType) nVT;
1297-
if (SVT.getVectorElementType() == EltVT &&
1298-
SVT.isScalableVector() == IsScalable &&
1299-
SVT.getVectorElementCount().Min > EC.Min && isTypeLegal(SVT)) {
1297+
if (SVT.getVectorElementType() == EltVT
1298+
&& SVT.getVectorNumElements() > NElts
1299+
&& SVT.isScalableVector() == IsScalable && isTypeLegal(SVT)) {
13001300
TransformToType[i] = SVT;
13011301
RegisterTypeForVT[i] = SVT;
13021302
NumRegistersForVT[i] = 1;
@@ -1340,12 +1340,10 @@ void TargetLoweringBase::computeRegisterProperties(
13401340
ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
13411341
else if (PreferredAction == TypeSplitVector)
13421342
ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1343-
else if (EC.Min > 1)
1344-
ValueTypeActions.setTypeAction(VT, TypeSplitVector);
13451343
else
1346-
ValueTypeActions.setTypeAction(VT, EC.Scalable
1347-
? TypeScalarizeScalableVector
1348-
: TypeScalarizeVector);
1344+
// Set type action according to the number of elements.
1345+
ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector
1346+
: TypeSplitVector);
13491347
} else {
13501348
TransformToType[i] = NVT;
13511349
ValueTypeActions.setTypeAction(VT, TypeWidenVector);

llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp

Lines changed: 6 additions & 67 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,9 @@
1717
#include "llvm/Target/TargetMachine.h"
1818
#include "gtest/gtest.h"
1919

20-
namespace llvm {
20+
using namespace llvm;
21+
22+
namespace {
2123

2224
class AArch64SelectionDAGTest : public testing::Test {
2325
protected:
@@ -39,8 +41,8 @@ class AArch64SelectionDAGTest : public testing::Test {
3941
return;
4042

4143
TargetOptions Options;
42-
TM = std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
43-
T->createTargetMachine("AArch64", "", "+sve", Options, None, None,
44+
TM = std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine*>(
45+
T->createTargetMachine("AArch64", "", "", Options, None, None,
4446
CodeGenOpt::Aggressive)));
4547
if (!TM)
4648
return;
@@ -67,14 +69,6 @@ class AArch64SelectionDAGTest : public testing::Test {
6769
DAG->init(*MF, ORE, nullptr, nullptr, nullptr, nullptr, nullptr);
6870
}
6971

70-
TargetLoweringBase::LegalizeTypeAction getTypeAction(EVT VT) {
71-
return DAG->getTargetLoweringInfo().getTypeAction(Context, VT);
72-
}
73-
74-
EVT getTypeToTransformTo(EVT VT) {
75-
return DAG->getTargetLoweringInfo().getTypeToTransformTo(Context, VT);
76-
}
77-
7872
LLVMContext Context;
7973
std::unique_ptr<LLVMTargetMachine> TM;
8074
std::unique_ptr<Module> M;
@@ -383,59 +377,4 @@ TEST_F(AArch64SelectionDAGTest, getSplatSourceVector_Scalable_ADD_of_SPLAT_VECTO
383377
EXPECT_EQ(SplatIdx, 0);
384378
}
385379

386-
TEST_F(AArch64SelectionDAGTest, getTypeConversion_SplitScalableMVT) {
387-
if (!TM)
388-
return;
389-
390-
MVT VT = MVT::nxv4i64;
391-
EXPECT_EQ(getTypeAction(VT), TargetLoweringBase::TypeSplitVector);
392-
ASSERT_TRUE(getTypeToTransformTo(VT).isScalableVector());
393-
}
394-
395-
TEST_F(AArch64SelectionDAGTest, getTypeConversion_PromoteScalableMVT) {
396-
if (!TM)
397-
return;
398-
399-
MVT VT = MVT::nxv2i32;
400-
EXPECT_EQ(getTypeAction(VT), TargetLoweringBase::TypePromoteInteger);
401-
ASSERT_TRUE(getTypeToTransformTo(VT).isScalableVector());
402-
}
403-
404-
TEST_F(AArch64SelectionDAGTest, getTypeConversion_NoScalarizeMVT_nxv1f32) {
405-
if (!TM)
406-
return;
407-
408-
MVT VT = MVT::nxv1f32;
409-
EXPECT_NE(getTypeAction(VT), TargetLoweringBase::TypeScalarizeVector);
410-
ASSERT_TRUE(getTypeToTransformTo(VT).isScalableVector());
411-
}
412-
413-
TEST_F(AArch64SelectionDAGTest, getTypeConversion_SplitScalableEVT) {
414-
if (!TM)
415-
return;
416-
417-
EVT VT = EVT::getVectorVT(Context, MVT::i64, 256, true);
418-
EXPECT_EQ(getTypeAction(VT), TargetLoweringBase::TypeSplitVector);
419-
EXPECT_EQ(getTypeToTransformTo(VT), VT.getHalfNumVectorElementsVT(Context));
420-
}
421-
422-
TEST_F(AArch64SelectionDAGTest, getTypeConversion_WidenScalableEVT) {
423-
if (!TM)
424-
return;
425-
426-
EVT FromVT = EVT::getVectorVT(Context, MVT::i64, 6, true);
427-
EVT ToVT = EVT::getVectorVT(Context, MVT::i64, 8, true);
428-
429-
EXPECT_EQ(getTypeAction(FromVT), TargetLoweringBase::TypeWidenVector);
430-
EXPECT_EQ(getTypeToTransformTo(FromVT), ToVT);
431-
}
432-
433-
TEST_F(AArch64SelectionDAGTest, getTypeConversion_NoScalarizeEVT_nxv1f128) {
434-
if (!TM)
435-
return;
436-
437-
EVT FromVT = EVT::getVectorVT(Context, MVT::f128, 1, true);
438-
EXPECT_DEATH(getTypeAction(FromVT), "Cannot legalize this vector");
439-
}
440-
441-
} // end namespace llvm
380+
} // end anonymous namespace

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