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[InstCombine][X86] Add addsub tests showing failure to simplify demandedelts (PR46277)
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‎llvm/test/Transforms/InstCombine/X86/x86-addsub.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -mtriple=x86_64-unknown-unknown -S | FileCheck %s
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declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>)
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declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>)
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declare <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double>, <4 x double>)
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declare <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float>, <8 x float>)
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;
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; Demanded Elts
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;
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define double @elts_addsub_v2f64(<2 x double> %0, <2 x double> %1) {
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; CHECK-LABEL: @elts_addsub_v2f64(
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; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP0:%.*]], <2 x double> undef, <2 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP1:%.*]], <2 x double> undef, <2 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP5:%.*]] = tail call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> [[TMP3]], <2 x double> [[TMP4]])
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; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x double> [[TMP5]], i32 0
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; CHECK-NEXT: ret double [[TMP6]]
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;
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%3 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> <i32 0, i32 0>
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%4 = shufflevector <2 x double> %1, <2 x double> undef, <2 x i32> <i32 0, i32 0>
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%5 = tail call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %3, <2 x double> %4)
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%6 = extractelement <2 x double> %5, i32 0
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ret double %6
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}
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define float @elts_addsub_v4f32(<4 x float> %0, <4 x float> %1) {
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; CHECK-LABEL: @elts_addsub_v4f32(
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; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x float> [[TMP0:%.*]], <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
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; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x float> [[TMP1:%.*]], <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
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; CHECK-NEXT: [[TMP5:%.*]] = tail call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> [[TMP3]], <4 x float> [[TMP4]])
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; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x float> [[TMP5]], <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: [[TMP7:%.*]] = fadd <4 x float> [[TMP5]], [[TMP6]]
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; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x float> [[TMP7]], i32 0
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; CHECK-NEXT: ret float [[TMP8]]
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;
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%3 = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
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%4 = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
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%5 = tail call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %3, <4 x float> %4)
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%6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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%7 = fadd <4 x float> %5, %6
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%8 = extractelement <4 x float> %7, i32 0
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ret float %8
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}
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define double @elts_addsub_v4f64(<4 x double> %0, <4 x double> %1) {
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; CHECK-LABEL: @elts_addsub_v4f64(
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; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x double> [[TMP0:%.*]], <4 x double> undef, <4 x i32> <i32 0, i32 1, i32 3, i32 3>
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; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x double> [[TMP1:%.*]], <4 x double> undef, <4 x i32> <i32 0, i32 1, i32 3, i32 3>
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; CHECK-NEXT: [[TMP5:%.*]] = tail call <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double> [[TMP3]], <4 x double> [[TMP4]])
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; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x double> [[TMP5]], i32 0
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; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x double> [[TMP5]], i32 1
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; CHECK-NEXT: [[TMP8:%.*]] = fadd double [[TMP6]], [[TMP7]]
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; CHECK-NEXT: ret double [[TMP8]]
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;
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%3 = shufflevector <4 x double> %0, <4 x double> undef, <4 x i32> <i32 0, i32 1, i32 3, i32 3>
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%4 = shufflevector <4 x double> %1, <4 x double> undef, <4 x i32> <i32 0, i32 1, i32 3, i32 3>
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%5 = tail call <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double> %3, <4 x double> %4)
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%6 = extractelement <4 x double> %5, i32 0
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%7 = extractelement <4 x double> %5, i32 1
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%8 = fadd double %6, %7
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ret double %8
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}
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define float @elts_addsub_v8f32(<8 x float> %0, <8 x float> %1) {
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; CHECK-LABEL: @elts_addsub_v8f32(
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; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x float> [[TMP0:%.*]], <8 x float> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 4, i32 4, i32 4>
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; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x float> [[TMP1:%.*]], <8 x float> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 4, i32 4, i32 4>
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; CHECK-NEXT: [[TMP5:%.*]] = tail call <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float> [[TMP3]], <8 x float> [[TMP4]])
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; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x float> [[TMP5]], i32 0
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; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x float> [[TMP5]], i32 1
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; CHECK-NEXT: [[TMP8:%.*]] = fadd float [[TMP6]], [[TMP7]]
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; CHECK-NEXT: ret float [[TMP8]]
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;
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%3 = shufflevector <8 x float> %0, <8 x float> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 4, i32 4, i32 4>
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%4 = shufflevector <8 x float> %1, <8 x float> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 4, i32 4, i32 4>
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%5 = tail call <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float> %3, <8 x float> %4)
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%6 = extractelement <8 x float> %5, i32 0
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%7 = extractelement <8 x float> %5, i32 1
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%8 = fadd float %6, %7
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ret float %8
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}
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