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SahilPatidarSahilPatidar
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[DAG] Fix Failure to reassociate SMAX/SMIN/UMAX/UMIN (llvm#82175)
Resolve llvm#58110
1 parent 03588a2 commit 9e0f590

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7 files changed

+127
-134
lines changed

7 files changed

+127
-134
lines changed

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5562,6 +5562,10 @@ SDValue DAGCombiner::visitIMINMAX(SDNode *N) {
55625562
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL))
55635563
return FoldedVOp;
55645564

5565+
// reassociate minmax
5566+
if (SDValue RMINMAX = reassociateOps(Opcode, DL, N0, N1, N->getFlags()))
5567+
return RMINMAX;
5568+
55655569
// Is sign bits are zero, flip between UMIN/UMAX and SMIN/SMAX.
55665570
// Only do this if the current op isn't legal and the flipped is.
55675571
if (!TLI.isOperationLegal(Opcode, VT) &&

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll

Lines changed: 42 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -549,36 +549,36 @@ define <33 x double> @strided_load_v33f64(ptr %ptr, i64 %stride, <33 x i1> %mask
549549
; CHECK-RV32-NEXT: # %bb.1:
550550
; CHECK-RV32-NEXT: li a3, 32
551551
; CHECK-RV32-NEXT: .LBB42_2:
552-
; CHECK-RV32-NEXT: mul a5, a3, a2
553-
; CHECK-RV32-NEXT: addi a6, a4, -32
554-
; CHECK-RV32-NEXT: sltu a4, a4, a6
555-
; CHECK-RV32-NEXT: addi a4, a4, -1
556-
; CHECK-RV32-NEXT: and a6, a4, a6
557-
; CHECK-RV32-NEXT: li a4, 16
558-
; CHECK-RV32-NEXT: add a5, a1, a5
559-
; CHECK-RV32-NEXT: bltu a6, a4, .LBB42_4
552+
; CHECK-RV32-NEXT: mul a6, a3, a2
553+
; CHECK-RV32-NEXT: addi a5, a4, -32
554+
; CHECK-RV32-NEXT: sltu a7, a4, a5
555+
; CHECK-RV32-NEXT: addi a7, a7, -1
556+
; CHECK-RV32-NEXT: and a7, a7, a5
557+
; CHECK-RV32-NEXT: li a5, 16
558+
; CHECK-RV32-NEXT: add a6, a1, a6
559+
; CHECK-RV32-NEXT: bltu a7, a5, .LBB42_4
560560
; CHECK-RV32-NEXT: # %bb.3:
561-
; CHECK-RV32-NEXT: li a6, 16
561+
; CHECK-RV32-NEXT: li a7, 16
562562
; CHECK-RV32-NEXT: .LBB42_4:
563563
; CHECK-RV32-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
564564
; CHECK-RV32-NEXT: vslidedown.vi v0, v8, 4
565-
; CHECK-RV32-NEXT: vsetvli zero, a6, e64, m8, ta, ma
566-
; CHECK-RV32-NEXT: vlse64.v v16, (a5), a2, v0.t
567-
; CHECK-RV32-NEXT: addi a5, a3, -16
568-
; CHECK-RV32-NEXT: sltu a6, a3, a5
569-
; CHECK-RV32-NEXT: addi a6, a6, -1
570-
; CHECK-RV32-NEXT: and a5, a6, a5
571-
; CHECK-RV32-NEXT: bltu a3, a4, .LBB42_6
565+
; CHECK-RV32-NEXT: vsetvli zero, a7, e64, m8, ta, ma
566+
; CHECK-RV32-NEXT: vlse64.v v16, (a6), a2, v0.t
567+
; CHECK-RV32-NEXT: addi a6, a3, -16
568+
; CHECK-RV32-NEXT: sltu a3, a3, a6
569+
; CHECK-RV32-NEXT: addi a3, a3, -1
570+
; CHECK-RV32-NEXT: and a3, a3, a6
571+
; CHECK-RV32-NEXT: bltu a4, a5, .LBB42_6
572572
; CHECK-RV32-NEXT: # %bb.5:
573-
; CHECK-RV32-NEXT: li a3, 16
573+
; CHECK-RV32-NEXT: li a4, 16
574574
; CHECK-RV32-NEXT: .LBB42_6:
575-
; CHECK-RV32-NEXT: mul a4, a3, a2
576-
; CHECK-RV32-NEXT: add a4, a1, a4
575+
; CHECK-RV32-NEXT: mul a5, a4, a2
576+
; CHECK-RV32-NEXT: add a5, a1, a5
577577
; CHECK-RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
578578
; CHECK-RV32-NEXT: vslidedown.vi v0, v8, 2
579-
; CHECK-RV32-NEXT: vsetvli zero, a5, e64, m8, ta, ma
580-
; CHECK-RV32-NEXT: vlse64.v v24, (a4), a2, v0.t
581579
; CHECK-RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
580+
; CHECK-RV32-NEXT: vlse64.v v24, (a5), a2, v0.t
581+
; CHECK-RV32-NEXT: vsetvli zero, a4, e64, m8, ta, ma
582582
; CHECK-RV32-NEXT: vmv1r.v v0, v8
583583
; CHECK-RV32-NEXT: vlse64.v v8, (a1), a2, v0.t
584584
; CHECK-RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
@@ -599,36 +599,36 @@ define <33 x double> @strided_load_v33f64(ptr %ptr, i64 %stride, <33 x i1> %mask
599599
; CHECK-RV64-NEXT: # %bb.1:
600600
; CHECK-RV64-NEXT: li a4, 32
601601
; CHECK-RV64-NEXT: .LBB42_2:
602-
; CHECK-RV64-NEXT: mul a5, a4, a2
603-
; CHECK-RV64-NEXT: addi a6, a3, -32
604-
; CHECK-RV64-NEXT: sltu a3, a3, a6
605-
; CHECK-RV64-NEXT: addi a3, a3, -1
606-
; CHECK-RV64-NEXT: and a6, a3, a6
607-
; CHECK-RV64-NEXT: li a3, 16
608-
; CHECK-RV64-NEXT: add a5, a1, a5
609-
; CHECK-RV64-NEXT: bltu a6, a3, .LBB42_4
602+
; CHECK-RV64-NEXT: mul a6, a4, a2
603+
; CHECK-RV64-NEXT: addi a5, a3, -32
604+
; CHECK-RV64-NEXT: sltu a7, a3, a5
605+
; CHECK-RV64-NEXT: addi a7, a7, -1
606+
; CHECK-RV64-NEXT: and a7, a7, a5
607+
; CHECK-RV64-NEXT: li a5, 16
608+
; CHECK-RV64-NEXT: add a6, a1, a6
609+
; CHECK-RV64-NEXT: bltu a7, a5, .LBB42_4
610610
; CHECK-RV64-NEXT: # %bb.3:
611-
; CHECK-RV64-NEXT: li a6, 16
611+
; CHECK-RV64-NEXT: li a7, 16
612612
; CHECK-RV64-NEXT: .LBB42_4:
613613
; CHECK-RV64-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
614614
; CHECK-RV64-NEXT: vslidedown.vi v0, v8, 4
615-
; CHECK-RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma
616-
; CHECK-RV64-NEXT: vlse64.v v16, (a5), a2, v0.t
617-
; CHECK-RV64-NEXT: addi a5, a4, -16
618-
; CHECK-RV64-NEXT: sltu a6, a4, a5
619-
; CHECK-RV64-NEXT: addi a6, a6, -1
620-
; CHECK-RV64-NEXT: and a5, a6, a5
621-
; CHECK-RV64-NEXT: bltu a4, a3, .LBB42_6
615+
; CHECK-RV64-NEXT: vsetvli zero, a7, e64, m8, ta, ma
616+
; CHECK-RV64-NEXT: vlse64.v v16, (a6), a2, v0.t
617+
; CHECK-RV64-NEXT: addi a6, a4, -16
618+
; CHECK-RV64-NEXT: sltu a4, a4, a6
619+
; CHECK-RV64-NEXT: addi a4, a4, -1
620+
; CHECK-RV64-NEXT: and a4, a4, a6
621+
; CHECK-RV64-NEXT: bltu a3, a5, .LBB42_6
622622
; CHECK-RV64-NEXT: # %bb.5:
623-
; CHECK-RV64-NEXT: li a4, 16
623+
; CHECK-RV64-NEXT: li a3, 16
624624
; CHECK-RV64-NEXT: .LBB42_6:
625-
; CHECK-RV64-NEXT: mul a3, a4, a2
626-
; CHECK-RV64-NEXT: add a3, a1, a3
625+
; CHECK-RV64-NEXT: mul a5, a3, a2
626+
; CHECK-RV64-NEXT: add a5, a1, a5
627627
; CHECK-RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
628628
; CHECK-RV64-NEXT: vslidedown.vi v0, v8, 2
629-
; CHECK-RV64-NEXT: vsetvli zero, a5, e64, m8, ta, ma
630-
; CHECK-RV64-NEXT: vlse64.v v24, (a3), a2, v0.t
631629
; CHECK-RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
630+
; CHECK-RV64-NEXT: vlse64.v v24, (a5), a2, v0.t
631+
; CHECK-RV64-NEXT: vsetvli zero, a3, e64, m8, ta, ma
632632
; CHECK-RV64-NEXT: vmv1r.v v0, v8
633633
; CHECK-RV64-NEXT: vlse64.v v8, (a1), a2, v0.t
634634
; CHECK-RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll

Lines changed: 62 additions & 59 deletions
Original file line numberDiff line numberDiff line change
@@ -310,23 +310,24 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
310310
; CHECK-NEXT: add a5, sp, a5
311311
; CHECK-NEXT: addi a5, a5, 16
312312
; CHECK-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
313+
; CHECK-NEXT: mv a6, a7
313314
; CHECK-NEXT: bltu a7, a3, .LBB16_4
314315
; CHECK-NEXT: # %bb.3:
315-
; CHECK-NEXT: li a7, 64
316+
; CHECK-NEXT: li a6, 64
316317
; CHECK-NEXT: .LBB16_4:
317318
; CHECK-NEXT: addi a5, a1, 384
318319
; CHECK-NEXT: li a3, 32
319320
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
320321
; CHECK-NEXT: vle64.v v8, (a1)
321-
; CHECK-NEXT: csrr a6, vlenb
322-
; CHECK-NEXT: slli a6, a6, 3
323-
; CHECK-NEXT: add a6, sp, a6
324-
; CHECK-NEXT: addi a6, a6, 16
325-
; CHECK-NEXT: vs8r.v v8, (a6) # Unknown-size Folded Spill
326-
; CHECK-NEXT: addi a6, a7, -32
327-
; CHECK-NEXT: sltu t0, a7, a6
328-
; CHECK-NEXT: addi t0, t0, -1
329-
; CHECK-NEXT: and a6, t0, a6
322+
; CHECK-NEXT: csrr t0, vlenb
323+
; CHECK-NEXT: slli t0, t0, 3
324+
; CHECK-NEXT: add t0, sp, t0
325+
; CHECK-NEXT: addi t0, t0, 16
326+
; CHECK-NEXT: vs8r.v v8, (t0) # Unknown-size Folded Spill
327+
; CHECK-NEXT: addi t0, a6, -32
328+
; CHECK-NEXT: sltu a6, a6, t0
329+
; CHECK-NEXT: addi a6, a6, -1
330+
; CHECK-NEXT: and a6, a6, t0
330331
; CHECK-NEXT: addi t0, a6, -16
331332
; CHECK-NEXT: sltu t1, a6, t0
332333
; CHECK-NEXT: addi t1, t1, -1
@@ -364,14 +365,15 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
364365
; CHECK-NEXT: add a5, sp, a5
365366
; CHECK-NEXT: addi a5, a5, 16
366367
; CHECK-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
368+
; CHECK-NEXT: mv a5, a4
367369
; CHECK-NEXT: bltu a4, a3, .LBB16_8
368370
; CHECK-NEXT: # %bb.7:
369-
; CHECK-NEXT: li a4, 32
371+
; CHECK-NEXT: li a5, 32
370372
; CHECK-NEXT: .LBB16_8:
371373
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
372374
; CHECK-NEXT: vle64.v v24, (a1)
373-
; CHECK-NEXT: addi a1, a4, -16
374-
; CHECK-NEXT: sltu a5, a4, a1
375+
; CHECK-NEXT: addi a1, a5, -16
376+
; CHECK-NEXT: sltu a5, a5, a1
375377
; CHECK-NEXT: addi a5, a5, -1
376378
; CHECK-NEXT: and a1, a5, a1
377379
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
@@ -387,62 +389,63 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
387389
; CHECK-NEXT: vmv1r.v v0, v5
388390
; CHECK-NEXT: vnsrl.wi v8, v24, 0, v0.t
389391
; CHECK-NEXT: vmv.v.v v0, v8
392+
; CHECK-NEXT: mv a1, a7
390393
; CHECK-NEXT: bltu a7, a3, .LBB16_12
391394
; CHECK-NEXT: # %bb.11:
392-
; CHECK-NEXT: li a7, 32
395+
; CHECK-NEXT: li a1, 32
393396
; CHECK-NEXT: .LBB16_12:
394397
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
395-
; CHECK-NEXT: csrr a1, vlenb
396-
; CHECK-NEXT: li a4, 24
397-
; CHECK-NEXT: mul a1, a1, a4
398-
; CHECK-NEXT: add a1, sp, a1
399-
; CHECK-NEXT: addi a1, a1, 16
400-
; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
398+
; CHECK-NEXT: csrr a4, vlenb
399+
; CHECK-NEXT: li a5, 24
400+
; CHECK-NEXT: mul a4, a4, a5
401+
; CHECK-NEXT: add a4, sp, a4
402+
; CHECK-NEXT: addi a4, a4, 16
403+
; CHECK-NEXT: vl8r.v v8, (a4) # Unknown-size Folded Reload
401404
; CHECK-NEXT: vmv4r.v v24, v8
402-
; CHECK-NEXT: csrr a1, vlenb
403-
; CHECK-NEXT: li a4, 56
404-
; CHECK-NEXT: mul a1, a1, a4
405-
; CHECK-NEXT: add a1, sp, a1
406-
; CHECK-NEXT: addi a1, a1, 16
407-
; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
405+
; CHECK-NEXT: csrr a4, vlenb
406+
; CHECK-NEXT: li a5, 56
407+
; CHECK-NEXT: mul a4, a4, a5
408+
; CHECK-NEXT: add a4, sp, a4
409+
; CHECK-NEXT: addi a4, a4, 16
410+
; CHECK-NEXT: vl8r.v v8, (a4) # Unknown-size Folded Reload
408411
; CHECK-NEXT: vslideup.vi v8, v24, 16
409-
; CHECK-NEXT: csrr a1, vlenb
410-
; CHECK-NEXT: li a4, 56
411-
; CHECK-NEXT: mul a1, a1, a4
412-
; CHECK-NEXT: add a1, sp, a1
413-
; CHECK-NEXT: addi a1, a1, 16
414-
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
415-
; CHECK-NEXT: csrr a1, vlenb
416-
; CHECK-NEXT: slli a1, a1, 4
417-
; CHECK-NEXT: add a1, sp, a1
418-
; CHECK-NEXT: addi a1, a1, 16
419-
; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
412+
; CHECK-NEXT: csrr a4, vlenb
413+
; CHECK-NEXT: li a5, 56
414+
; CHECK-NEXT: mul a4, a4, a5
415+
; CHECK-NEXT: add a4, sp, a4
416+
; CHECK-NEXT: addi a4, a4, 16
417+
; CHECK-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
418+
; CHECK-NEXT: csrr a4, vlenb
419+
; CHECK-NEXT: slli a4, a4, 4
420+
; CHECK-NEXT: add a4, sp, a4
421+
; CHECK-NEXT: addi a4, a4, 16
422+
; CHECK-NEXT: vl8r.v v8, (a4) # Unknown-size Folded Reload
420423
; CHECK-NEXT: vmv4r.v v24, v8
421-
; CHECK-NEXT: csrr a1, vlenb
422-
; CHECK-NEXT: li a4, 48
423-
; CHECK-NEXT: mul a1, a1, a4
424-
; CHECK-NEXT: add a1, sp, a1
425-
; CHECK-NEXT: addi a1, a1, 16
426-
; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
424+
; CHECK-NEXT: csrr a4, vlenb
425+
; CHECK-NEXT: li a5, 48
426+
; CHECK-NEXT: mul a4, a4, a5
427+
; CHECK-NEXT: add a4, sp, a4
428+
; CHECK-NEXT: addi a4, a4, 16
429+
; CHECK-NEXT: vl8r.v v8, (a4) # Unknown-size Folded Reload
427430
; CHECK-NEXT: vslideup.vi v8, v24, 16
428-
; CHECK-NEXT: csrr a1, vlenb
429-
; CHECK-NEXT: li a4, 48
430-
; CHECK-NEXT: mul a1, a1, a4
431-
; CHECK-NEXT: add a1, sp, a1
432-
; CHECK-NEXT: addi a1, a1, 16
433-
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
431+
; CHECK-NEXT: csrr a4, vlenb
432+
; CHECK-NEXT: li a5, 48
433+
; CHECK-NEXT: mul a4, a4, a5
434+
; CHECK-NEXT: add a4, sp, a4
435+
; CHECK-NEXT: addi a4, a4, 16
436+
; CHECK-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
434437
; CHECK-NEXT: vmv4r.v v8, v0
435438
; CHECK-NEXT: vslideup.vi v8, v16, 16
436-
; CHECK-NEXT: csrr a1, vlenb
437-
; CHECK-NEXT: li a4, 24
438-
; CHECK-NEXT: mul a1, a1, a4
439-
; CHECK-NEXT: add a1, sp, a1
440-
; CHECK-NEXT: addi a1, a1, 16
441-
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
442-
; CHECK-NEXT: addi a1, a7, -16
443-
; CHECK-NEXT: sltu a4, a7, a1
444-
; CHECK-NEXT: addi a4, a4, -1
445-
; CHECK-NEXT: and a1, a4, a1
439+
; CHECK-NEXT: csrr a4, vlenb
440+
; CHECK-NEXT: li a5, 24
441+
; CHECK-NEXT: mul a4, a4, a5
442+
; CHECK-NEXT: add a4, sp, a4
443+
; CHECK-NEXT: addi a4, a4, 16
444+
; CHECK-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
445+
; CHECK-NEXT: addi a4, a1, -16
446+
; CHECK-NEXT: sltu a1, a1, a4
447+
; CHECK-NEXT: addi a1, a1, -1
448+
; CHECK-NEXT: and a1, a1, a4
446449
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
447450
; CHECK-NEXT: vmv1r.v v0, v6
448451
; CHECK-NEXT: csrr a1, vlenb

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -418,20 +418,20 @@ define <33 x double> @vpload_v33f64(ptr %ptr, <33 x i1> %m, i32 zeroext %evl) {
418418
; CHECK-NEXT: li a3, 32
419419
; CHECK-NEXT: .LBB32_2:
420420
; CHECK-NEXT: addi a4, a3, -16
421-
; CHECK-NEXT: sltu a5, a3, a4
422-
; CHECK-NEXT: addi a5, a5, -1
423-
; CHECK-NEXT: and a4, a5, a4
424-
; CHECK-NEXT: addi a5, a1, 128
421+
; CHECK-NEXT: sltu a3, a3, a4
422+
; CHECK-NEXT: addi a3, a3, -1
423+
; CHECK-NEXT: and a3, a3, a4
424+
; CHECK-NEXT: addi a4, a1, 128
425425
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
426426
; CHECK-NEXT: vslidedown.vi v0, v8, 2
427-
; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
428-
; CHECK-NEXT: vle64.v v16, (a5), v0.t
429-
; CHECK-NEXT: addi a4, a2, -32
430-
; CHECK-NEXT: sltu a2, a2, a4
431-
; CHECK-NEXT: addi a2, a2, -1
432-
; CHECK-NEXT: and a4, a2, a4
433-
; CHECK-NEXT: li a2, 16
434-
; CHECK-NEXT: bltu a4, a2, .LBB32_4
427+
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
428+
; CHECK-NEXT: vle64.v v16, (a4), v0.t
429+
; CHECK-NEXT: addi a3, a2, -32
430+
; CHECK-NEXT: sltu a4, a2, a3
431+
; CHECK-NEXT: addi a4, a4, -1
432+
; CHECK-NEXT: and a4, a4, a3
433+
; CHECK-NEXT: li a3, 16
434+
; CHECK-NEXT: bltu a4, a3, .LBB32_4
435435
; CHECK-NEXT: # %bb.3:
436436
; CHECK-NEXT: li a4, 16
437437
; CHECK-NEXT: .LBB32_4:
@@ -440,11 +440,11 @@ define <33 x double> @vpload_v33f64(ptr %ptr, <33 x i1> %m, i32 zeroext %evl) {
440440
; CHECK-NEXT: vslidedown.vi v0, v8, 4
441441
; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
442442
; CHECK-NEXT: vle64.v v24, (a5), v0.t
443-
; CHECK-NEXT: bltu a3, a2, .LBB32_6
443+
; CHECK-NEXT: bltu a2, a3, .LBB32_6
444444
; CHECK-NEXT: # %bb.5:
445-
; CHECK-NEXT: li a3, 16
445+
; CHECK-NEXT: li a2, 16
446446
; CHECK-NEXT: .LBB32_6:
447-
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
447+
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
448448
; CHECK-NEXT: vmv1r.v v0, v8
449449
; CHECK-NEXT: vle64.v v8, (a1), v0.t
450450
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma

‎llvm/test/CodeGen/X86/combine-smin.ll

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -70,9 +70,6 @@ define <16 x i8> @test_v16i8_reassociation(<16 x i8> %a) {
7070
; SSE2-LABEL: test_v16i8_reassociation:
7171
; SSE2: # %bb.0:
7272
; SSE2-NEXT: pxor %xmm1, %xmm1
73-
; SSE2-NEXT: pxor %xmm2, %xmm2
74-
; SSE2-NEXT: pcmpgtb %xmm0, %xmm2
75-
; SSE2-NEXT: pand %xmm2, %xmm0
7673
; SSE2-NEXT: pcmpgtb %xmm0, %xmm1
7774
; SSE2-NEXT: pand %xmm1, %xmm0
7875
; SSE2-NEXT: retq
@@ -81,21 +78,18 @@ define <16 x i8> @test_v16i8_reassociation(<16 x i8> %a) {
8178
; SSE41: # %bb.0:
8279
; SSE41-NEXT: pxor %xmm1, %xmm1
8380
; SSE41-NEXT: pminsb %xmm1, %xmm0
84-
; SSE41-NEXT: pminsb %xmm1, %xmm0
8581
; SSE41-NEXT: retq
8682
;
8783
; SSE42-LABEL: test_v16i8_reassociation:
8884
; SSE42: # %bb.0:
8985
; SSE42-NEXT: pxor %xmm1, %xmm1
9086
; SSE42-NEXT: pminsb %xmm1, %xmm0
91-
; SSE42-NEXT: pminsb %xmm1, %xmm0
9287
; SSE42-NEXT: retq
9388
;
9489
; AVX-LABEL: test_v16i8_reassociation:
9590
; AVX: # %bb.0:
9691
; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
9792
; AVX-NEXT: vpminsb %xmm1, %xmm0, %xmm0
98-
; AVX-NEXT: vpminsb %xmm1, %xmm0, %xmm0
9993
; AVX-NEXT: retq
10094
%1 = call <16 x i8> @llvm.smin.v16i8(<16 x i8> %a, <16 x i8> zeroinitializer)
10195
%2 = call <16 x i8> @llvm.smin.v16i8(<16 x i8> %1, <16 x i8> zeroinitializer)

‎llvm/test/CodeGen/X86/combine-umax.ll

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -45,16 +45,12 @@ define <8 x i16> @test_v8i16_nosignbit(<8 x i16> %a, <8 x i16> %b) {
4545
define <16 x i8> @test_v16i8_reassociation(<16 x i8> %a) {
4646
; SSE-LABEL: test_v16i8_reassociation:
4747
; SSE: # %bb.0:
48-
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
49-
; SSE-NEXT: pmaxub %xmm1, %xmm0
50-
; SSE-NEXT: pmaxub %xmm1, %xmm0
48+
; SSE-NEXT: pmaxub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
5149
; SSE-NEXT: retq
5250
;
5351
; AVX-LABEL: test_v16i8_reassociation:
5452
; AVX: # %bb.0:
55-
; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
56-
; AVX-NEXT: vpmaxub %xmm1, %xmm0, %xmm0
57-
; AVX-NEXT: vpmaxub %xmm1, %xmm0, %xmm0
53+
; AVX-NEXT: vpmaxub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
5854
; AVX-NEXT: retq
5955
%1 = call <16 x i8> @llvm.umax.v16i8(<16 x i8> %a, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>)
6056
%2 = call <16 x i8> @llvm.umax.v16i8(<16 x i8> %1, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>)

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