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Merge commit '7840fa91a24e' from llvm.org/main into next
2 parents 4aa6551 + 7840fa9 commit 9e3338c

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llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

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@@ -1511,6 +1511,11 @@ void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) {
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return;
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}
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// If the AVL isn't used in its predecessors then bail, since we have no AVL
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// to insert a vsetvli with.
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if (AvailableInfo.hasAVLIgnored())
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return;
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// Model the effect of changing the input state of the block MBB to
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// AvailableInfo. We're looking for two issues here; one legality,
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// one profitability.

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir

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@@ -130,6 +130,10 @@
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ret void
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}
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define void @pre_undemanded_vl() {
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ret void
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}
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declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
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declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
@@ -1041,3 +1045,12 @@ body: |
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PseudoRET
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...
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---
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name: pre_undemanded_vl
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body: |
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bb.0:
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PseudoBR %bb.1
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bb.1:
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%x:gpr = PseudoVMV_X_S undef $noreg, 6
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PseudoBR %bb.1
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...

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