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Merge commit '8ebbf25cb1e9' from llvm.org/master into apple/master
2 parents af4132c + 8ebbf25 commit 9e82f87

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llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

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Original file line numberDiff line numberDiff line change
@@ -1349,6 +1349,8 @@ bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) {
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for (MachineBasicBlock *MBB : depth_first(&MF)) {
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MachineBasicBlock::iterator I, Next;
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MachineOperand *CurrentKnownM0Val = nullptr;
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for (I = MBB->begin(); I != MBB->end(); I = Next) {
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Next = std::next(I);
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MachineInstr &MI = *I;
@@ -1361,6 +1363,25 @@ bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) {
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if (IsIEEEMode || (!HasNSZ && !MI.getFlag(MachineInstr::FmNsz)) ||
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!tryFoldOMod(MI))
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tryFoldClamp(MI);
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// Saw an unknown clobber of m0, so we no longer know what it is.
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if (CurrentKnownM0Val && MI.modifiesRegister(AMDGPU::M0, TRI))
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CurrentKnownM0Val = nullptr;
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continue;
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}
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// Specially track simple redefs of m0 to the same value in a block, so we
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// can erase the later ones.
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if (MI.getOperand(0).getReg() == AMDGPU::M0) {
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MachineOperand &NewM0Val = MI.getOperand(1);
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if (CurrentKnownM0Val && CurrentKnownM0Val->isIdenticalTo(NewM0Val)) {
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MI.eraseFromParent();
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continue;
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}
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// We aren't tracking other physical registers
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CurrentKnownM0Val = (NewM0Val.isReg() && NewM0Val.getReg().isPhysical()) ?
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nullptr : &NewM0Val;
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continue;
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}
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