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[tests] Add coverage for SLP reschedule event
This is slightly reduced from the crash reported against D117951.
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -slp-vectorizer < %s | FileCheck %s
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declare void @use(double, double)
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; Create a situation where a previously scheduled instruction is encountered
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; again, and needs to be unscheduled.
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define void @test() {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: for.body602:
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; CHECK-NEXT: [[MUL701:%.*]] = fmul double 0.000000e+00, 0.000000e+00
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; CHECK-NEXT: [[MUL703:%.*]] = fmul double 0.000000e+00, 0.000000e+00
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; CHECK-NEXT: [[I4:%.*]] = call double @llvm.fmuladd.f64(double [[MUL701]], double 0.000000e+00, double [[MUL703]])
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; CHECK-NEXT: store double [[I4]], double* null, align 8
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; CHECK-NEXT: [[I5:%.*]] = load double, double* null, align 8
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; CHECK-NEXT: [[I6:%.*]] = load double, double* null, align 8
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; CHECK-NEXT: [[MUL746:%.*]] = fmul double 0.000000e+00, [[I6]]
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; CHECK-NEXT: [[MUL747:%.*]] = fmul double 0.000000e+00, [[I5]]
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; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[MUL746]], i32 0
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; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[MUL701]], i32 1
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; CHECK-NEXT: [[TMP2:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> zeroinitializer, <2 x double> zeroinitializer, <2 x double> [[TMP1]])
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; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> poison, double [[MUL747]], i32 0
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; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP3]], double [[MUL703]], i32 1
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; CHECK-NEXT: [[TMP5:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP2]], <2 x double> zeroinitializer, <2 x double> [[TMP4]])
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; CHECK-NEXT: [[TMP6:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP5]], <2 x double> zeroinitializer, <2 x double> zeroinitializer)
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; CHECK-NEXT: [[TMP7:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> zeroinitializer, <2 x double> [[TMP6]], <2 x double> zeroinitializer)
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; CHECK-NEXT: br label [[FOR_COND794_PREHEADER:%.*]]
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; CHECK: for.cond794.preheader:
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; CHECK-NEXT: [[TMP8:%.*]] = phi <2 x double> [ [[TMP7]], [[FOR_BODY602:%.*]] ]
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; CHECK-NEXT: ret void
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;
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for.body602:
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%mul701 = fmul double 0.000000e+00, 0.000000e+00
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%mul703 = fmul double 0.000000e+00, 0.000000e+00
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%i = call double @llvm.fmuladd.f64(double 0.000000e+00, double 0.000000e+00, double %mul701)
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%i1 = call double @llvm.fmuladd.f64(double %i, double 0.000000e+00, double %mul703)
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%i2 = call double @llvm.fmuladd.f64(double %i1, double 0.000000e+00, double 0.000000e+00)
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%i3 = call double @llvm.fmuladd.f64(double 0.000000e+00, double %i2, double 0.000000e+00)
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%i4 = call double @llvm.fmuladd.f64(double %mul701, double 0.000000e+00, double %mul703)
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store double %i4, double* null, align 8
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%i5 = load double, double* null, align 8
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%i6 = load double, double* null, align 8
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%mul746 = fmul double 0.000000e+00, %i6
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%mul747 = fmul double 0.000000e+00, %i5
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%i7 = call double @llvm.fmuladd.f64(double 0.000000e+00, double 0.000000e+00, double %mul746)
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%i8 = call double @llvm.fmuladd.f64(double %i7, double 0.000000e+00, double %mul747)
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%i9 = call double @llvm.fmuladd.f64(double %i8, double 0.000000e+00, double 0.000000e+00)
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%i10 = call double @llvm.fmuladd.f64(double 0.000000e+00, double %i9, double 0.000000e+00)
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br label %for.cond794.preheader
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for.cond794.preheader: ; preds = %for.body602
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%fullElectEnergy.1.lcssa = phi double [ %i10, %for.body602 ]
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%electEnergy.1.lcssa = phi double [ %i3, %for.body602 ]
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ret void
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}
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declare double @llvm.fmuladd.f64(double, double, double)

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