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[SVE][CodeGen] Fix TypeSize/ElementCount related warnings in sve-split-load.ll
I have fixed up a number of warnings resulting from TypeSize -> uint64_t casts and calling getVectorNumElements() on scalable vector types. I think most of the changes are fairly trivial except for those in DAGTypeLegalizer::SplitVecRes_MLOAD I've tried to ensure we create the MachineMemoryOperands in a sensible way for scalable vectors. I have added a CHECK line to the following test: CodeGen/AArch64/sve-split-load.ll that ensures no new warnings are added. Differential Revision: https://reviews.llvm.org/D86697
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6 files changed

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-21
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6 files changed

+40
-21
lines changed

‎llvm/include/llvm/Support/TypeSize.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,13 @@ class ElementCount {
4949
return { Min / RHS, Scalable };
5050
}
5151

52+
friend ElementCount operator-(const ElementCount &LHS,
53+
const ElementCount &RHS) {
54+
assert(LHS.Scalable == RHS.Scalable &&
55+
"Arithmetic using mixed scalable and fixed types");
56+
return {LHS.Min - RHS.Min, LHS.Scalable};
57+
}
58+
5259
bool operator==(const ElementCount& RHS) const {
5360
return Min == RHS.Min && Scalable == RHS.Scalable;
5461
}

‎llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -718,7 +718,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
718718

719719
LLVM_DEBUG(dbgs() << "Legalizing extending load operation\n");
720720
EVT SrcVT = LD->getMemoryVT();
721-
unsigned SrcWidth = SrcVT.getSizeInBits();
721+
TypeSize SrcWidth = SrcVT.getSizeInBits();
722722
MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
723723
AAMDNodes AAInfo = LD->getAAInfo();
724724

@@ -764,14 +764,15 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
764764

765765
Value = Result;
766766
Chain = Ch;
767-
} else if (SrcWidth & (SrcWidth - 1)) {
767+
} else if (!isPowerOf2_64(SrcWidth.getKnownMinSize())) {
768768
// If not loading a power-of-2 number of bits, expand as two loads.
769769
assert(!SrcVT.isVector() && "Unsupported extload!");
770-
unsigned LogSrcWidth = Log2_32(SrcWidth);
770+
unsigned SrcWidthBits = SrcWidth.getFixedSize();
771+
unsigned LogSrcWidth = Log2_32(SrcWidthBits);
771772
assert(LogSrcWidth < 32);
772773
unsigned RoundWidth = 1 << LogSrcWidth;
773-
assert(RoundWidth < SrcWidth);
774-
unsigned ExtraWidth = SrcWidth - RoundWidth;
774+
assert(RoundWidth < SrcWidthBits);
775+
unsigned ExtraWidth = SrcWidthBits - RoundWidth;
775776
assert(ExtraWidth < RoundWidth);
776777
assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
777778
"Load size not an integral number of bytes!");

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Lines changed: 13 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1638,9 +1638,10 @@ void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
16381638
else
16391639
std::tie(PassThruLo, PassThruHi) = DAG.SplitVector(PassThru, dl);
16401640

1641+
unsigned LoSize = MemoryLocation::getSizeOrUnknown(LoMemVT.getStoreSize());
16411642
MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
1642-
MLD->getPointerInfo(), MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1643-
Alignment, MLD->getAAInfo(), MLD->getRanges());
1643+
MLD->getPointerInfo(), MachineMemOperand::MOLoad, LoSize, Alignment,
1644+
MLD->getAAInfo(), MLD->getRanges());
16441645

16451646
Lo = DAG.getMaskedLoad(LoVT, dl, Ch, Ptr, Offset, MaskLo, PassThruLo, LoMemVT,
16461647
MMO, MLD->getAddressingMode(), ExtType,
@@ -1654,12 +1655,18 @@ void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
16541655
// Generate hi masked load.
16551656
Ptr = TLI.IncrementMemoryAddress(Ptr, MaskLo, dl, LoMemVT, DAG,
16561657
MLD->isExpandingLoad());
1657-
unsigned HiOffset = LoMemVT.getStoreSize();
1658+
unsigned HiSize = MemoryLocation::getSizeOrUnknown(HiMemVT.getStoreSize());
1659+
1660+
MachinePointerInfo MPI;
1661+
if (LoMemVT.isScalableVector())
1662+
MPI = MachinePointerInfo(MLD->getPointerInfo().getAddrSpace());
1663+
else
1664+
MPI = MLD->getPointerInfo().getWithOffset(
1665+
LoMemVT.getStoreSize().getFixedSize());
16581666

16591667
MMO = DAG.getMachineFunction().getMachineMemOperand(
1660-
MLD->getPointerInfo().getWithOffset(HiOffset),
1661-
MachineMemOperand::MOLoad, HiMemVT.getStoreSize(), Alignment,
1662-
MLD->getAAInfo(), MLD->getRanges());
1668+
MPI, MachineMemOperand::MOLoad, HiSize, Alignment, MLD->getAAInfo(),
1669+
MLD->getRanges());
16631670

16641671
Hi = DAG.getMaskedLoad(HiVT, dl, Ch, Ptr, Offset, MaskHi, PassThruHi,
16651672
HiMemVT, MMO, MLD->getAddressingMode(), ExtType,

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -6979,7 +6979,7 @@ SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
69796979
assert(VT.isVector() == MemVT.isVector() &&
69806980
"Cannot use an ext load to convert to or from a vector!");
69816981
assert((!VT.isVector() ||
6982-
VT.getVectorNumElements() == MemVT.getVectorNumElements()) &&
6982+
VT.getVectorElementCount() == MemVT.getVectorElementCount()) &&
69836983
"Cannot use an ext load to change the number of vector elements!");
69846984
}
69856985

@@ -9637,24 +9637,24 @@ std::pair<EVT, EVT>
96379637
SelectionDAG::GetDependentSplitDestVTs(const EVT &VT, const EVT &EnvVT,
96389638
bool *HiIsEmpty) const {
96399639
EVT EltTp = VT.getVectorElementType();
9640-
bool IsScalable = VT.isScalableVector();
96419640
// Examples:
96429641
// custom VL=8 with enveloping VL=8/8 yields 8/0 (hi empty)
96439642
// custom VL=9 with enveloping VL=8/8 yields 8/1
96449643
// custom VL=10 with enveloping VL=8/8 yields 8/2
96459644
// etc.
9646-
unsigned VTNumElts = VT.getVectorNumElements();
9647-
unsigned EnvNumElts = EnvVT.getVectorNumElements();
9645+
ElementCount VTNumElts = VT.getVectorElementCount();
9646+
ElementCount EnvNumElts = EnvVT.getVectorElementCount();
9647+
assert(VTNumElts.isScalable() == EnvNumElts.isScalable() &&
9648+
"Mixing fixed width and scalable vectors when enveloping a type");
96489649
EVT LoVT, HiVT;
9649-
if (VTNumElts > EnvNumElts) {
9650+
if (VTNumElts.getKnownMinValue() > EnvNumElts.getKnownMinValue()) {
96509651
LoVT = EnvVT;
9651-
HiVT = EVT::getVectorVT(*getContext(), EltTp, VTNumElts - EnvNumElts,
9652-
IsScalable);
9652+
HiVT = EVT::getVectorVT(*getContext(), EltTp, VTNumElts - EnvNumElts);
96539653
*HiIsEmpty = false;
96549654
} else {
96559655
// Flag that hi type has zero storage size, but return split envelop type
96569656
// (this would be easier if vector types with zero elements were allowed).
9657-
LoVT = EVT::getVectorVT(*getContext(), EltTp, VTNumElts, IsScalable);
9657+
LoVT = EVT::getVectorVT(*getContext(), EltTp, VTNumElts);
96589658
HiVT = EnvVT;
96599659
*HiIsEmpty = true;
96609660
}

‎llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7221,7 +7221,7 @@ TargetLowering::IncrementMemoryAddress(SDValue Addr, SDValue Mask,
72217221
SDValue Increment;
72227222
EVT AddrVT = Addr.getValueType();
72237223
EVT MaskVT = Mask.getValueType();
7224-
assert(DataVT.getVectorNumElements() == MaskVT.getVectorNumElements() &&
7224+
assert(DataVT.getVectorElementCount() == MaskVT.getVectorElementCount() &&
72257225
"Incompatible types of Data and Mask");
72267226
if (IsCompressedMemory) {
72277227
if (DataVT.isScalableVector())

‎llvm/test/CodeGen/AArch64/sve-split-load.ll

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,9 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
2+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
3+
; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
4+
5+
; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
6+
; WARN-NOT: warning
37

48
; UNPREDICATED
59

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