Revert for: [AMDGPU]: PHI Elimination hooks added for custom COPY insertion.

llvm-svn: 371873

Author: alex-t

llvm/include/llvm/CodeGen/TargetInstrInfo.h

@@ -22,7 +22,6 @@
 #include "llvm/CodeGen/MachineCombinerPattern.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineLoopInfo.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineOutliner.h"
@@ -1639,28 +1638,6 @@ class TargetInstrInfo : public MCInstrInfo {
     return false;
   }
 
-  /// During PHI eleimination lets target to make necessary checks and
-  /// insert the copy to the PHI destination register in a target specific
-  /// manner.
-  virtual MachineInstr *createPHIDestinationCopy(
-      MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt,
-      const DebugLoc &DL, Register Src, Register Dst) const {
-    return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
-        .addReg(Src);
-  }
-
-  /// During PHI eleimination lets target to make necessary checks and
-  /// insert the copy to the PHI destination register in a target specific
-  /// manner.
-  virtual MachineInstr *createPHISourceCopy(MachineBasicBlock &MBB,
-                                            MachineBasicBlock::iterator InsPt,
-                                            const DebugLoc &DL, Register Src,
-                                            Register SrcSubReg,
-                                            Register Dst) const {
-    return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
-        .addReg(Src, 0, SrcSubReg);
-  }
-
   /// Returns a \p outliner::OutlinedFunction struct containing target-specific
   /// information for a set of outlining candidates.
   virtual outliner::OutlinedFunction getOutliningCandidateInfo(

llvm/lib/CodeGen/PHIElimination.cpp

@@ -31,9 +31,7 @@
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SlotIndexes.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
-#include "llvm/CodeGen/TargetLowering.h"
 #include "llvm/CodeGen/TargetOpcodes.h"
-#include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Pass.h"
@@ -254,12 +252,11 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
   // Insert a register to register copy at the top of the current block (but
   // after any remaining phi nodes) which copies the new incoming register
   // into the phi node destination.
-  MachineInstr *PHICopy = nullptr;
   const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
   if (allPhiOperandsUndefined(*MPhi, *MRI))
     // If all sources of a PHI node are implicit_def or undef uses, just emit an
     // implicit_def instead of a copy.
-    PHICopy = BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
+    BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
             TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
   else {
     // Can we reuse an earlier PHI node? This only happens for critical edges,
@@ -276,13 +273,15 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
       const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
       entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
     }
-    // Give the target possiblity to handle special cases fallthrough otherwise
-    PHICopy = TII->createPHIDestinationCopy(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
-                                  IncomingReg, DestReg);
+    BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
+            TII->get(TargetOpcode::COPY), DestReg)
+      .addReg(IncomingReg);
   }
 
   // Update live variable information if there is any.
   if (LV) {
+    MachineInstr &PHICopy = *std::prev(AfterPHIsIt);
+
     if (IncomingReg) {
       LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg);
 
@@ -303,7 +302,7 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
       // killed.  Note that because the value is defined in several places (once
       // each for each incoming block), the "def" block and instruction fields
       // for the VarInfo is not filled in.
-      LV->addVirtualRegisterKilled(IncomingReg, *PHICopy);
+      LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
     }
 
     // Since we are going to be deleting the PHI node, if it is the last use of
@@ -313,14 +312,15 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
 
     // If the result is dead, update LV.
     if (isDead) {
-      LV->addVirtualRegisterDead(DestReg, *PHICopy);
+      LV->addVirtualRegisterDead(DestReg, PHICopy);
       LV->removeVirtualRegisterDead(DestReg, *MPhi);
     }
   }
 
   // Update LiveIntervals for the new copy or implicit def.
   if (LIS) {
-    SlotIndex DestCopyIndex = LIS->InsertMachineInstrInMaps(*PHICopy);
+    SlotIndex DestCopyIndex =
+        LIS->InsertMachineInstrInMaps(*std::prev(AfterPHIsIt));
 
     SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB);
     if (IncomingReg) {
@@ -406,9 +406,9 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
           if (DefMI->isImplicitDef())
             ImpDefs.insert(DefMI);
       } else {
-        NewSrcInstr =
-            TII->createPHISourceCopy(opBlock, InsertPos, MPhi->getDebugLoc(),
-                                     SrcReg, SrcSubReg, IncomingReg);
+        NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
+                            TII->get(TargetOpcode::COPY), IncomingReg)
+                        .addReg(SrcReg, 0, SrcSubReg);
       }
     }
 
@@ -457,7 +457,7 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
           }
         } else {
           // We just inserted this copy.
-          KillInst = NewSrcInstr;
+          KillInst = std::prev(InsertPos);
         }
       }
       assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction");

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

@@ -6410,33 +6410,3 @@ bool llvm::execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI,
       return true;
   }
 }
-
-MachineInstr *SIInstrInfo::createPHIDestinationCopy(
-    MachineBasicBlock &MBB, MachineBasicBlock::iterator LastPHIIt,
-    const DebugLoc &DL, Register Src, Register Dst) const {
-  auto Cur = MBB.begin();
-  while (Cur != MBB.end()) {
-    if (!Cur->isPHI() && Cur->readsRegister(Dst))
-      return BuildMI(MBB, Cur, DL, get(TargetOpcode::COPY), Dst).addReg(Src);
-    ++Cur;
-    if (Cur == LastPHIIt)
-      break;
-  }
-
-  return TargetInstrInfo::createPHIDestinationCopy(MBB, LastPHIIt, DL, Src,
-                                                   Dst);
-}
-
-MachineInstr *SIInstrInfo::createPHISourceCopy(
-    MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt,
-    const DebugLoc &DL, Register Src, Register SrcSubReg, Register Dst) const {
-  if (InsPt != MBB.end() && InsPt->isPseudo() && InsPt->definesRegister(Src)) {
-    InsPt++;
-    return BuildMI(MBB, InsPt, InsPt->getDebugLoc(), get(TargetOpcode::COPY),
-                   Dst)
-        .addReg(Src, 0, SrcSubReg)
-        .addReg(AMDGPU::EXEC, RegState::Implicit);
-  }
-  return TargetInstrInfo::createPHISourceCopy(MBB, InsPt, DL, Src, SrcSubReg,
-                                              Dst);
-}

llvm/lib/Target/AMDGPU/SIInstrInfo.h

@@ -954,17 +954,6 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
 
   bool isBasicBlockPrologue(const MachineInstr &MI) const override;
 
-  MachineInstr *createPHIDestinationCopy(MachineBasicBlock &MBB,
-                                         MachineBasicBlock::iterator InsPt,
-                                         const DebugLoc &DL, Register Src,
-                                         Register Dst) const override;
-
-  MachineInstr *createPHISourceCopy(MachineBasicBlock &MBB,
-                                    MachineBasicBlock::iterator InsPt,
-                                    const DebugLoc &DL, Register Src,
-                                    Register SrcSubReg,
-                                    Register Dst) const override;
-
   /// Return a partially built integer add instruction without carry.
   /// Caller must add source operands.
   /// For pre-GFX9 it will generate unused carry destination operand.

llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp

@@ -400,17 +400,13 @@ void SILowerControlFlow::emitLoop(MachineInstr &MI) {
 
 void SILowerControlFlow::emitEndCf(MachineInstr &MI) {
   MachineBasicBlock &MBB = *MI.getParent();
-  MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
-  unsigned CFMask = MI.getOperand(0).getReg();
-  MachineInstr *Def = MRI.getUniqueVRegDef(CFMask);
   const DebugLoc &DL = MI.getDebugLoc();
 
-  MachineBasicBlock::iterator InsPt =
-      Def && Def->getParent() == &MBB ? std::next(MachineBasicBlock::iterator(Def))
-                               : MBB.begin();
-  MachineInstr *NewMI = BuildMI(MBB, InsPt, DL, TII->get(OrOpc), Exec)
-                            .addReg(Exec)
-                            .add(MI.getOperand(0));
+  MachineBasicBlock::iterator InsPt = MBB.begin();
+  MachineInstr *NewMI =
+      BuildMI(MBB, InsPt, DL, TII->get(OrOpc), Exec)
+          .addReg(Exec)
+          .add(MI.getOperand(0));
 
   if (LIS)
     LIS->ReplaceMachineInstrInMaps(MI, *NewMI);

llvm/test/CodeGen/AMDGPU/phi-elimination-assertion.mir

@@ -26,8 +26,8 @@ body:             |
 
 # CHECK-LABEL: name:            foo
 # CHECK:   bb.3:
-# CHECK-NEXT:     dead %2:sreg_32_xm0 = IMPLICIT_DEF
 # CHECK-NEXT:     %3:sreg_32_xm0 = COPY killed %4
+# CHECK-NEXT:     dead %2:sreg_32_xm0 = IMPLICIT_DEF
 # CHECK-NEXT:     S_NOP 0, implicit killed %3