[RISCV] Made vcompress pseudoinstruction SEW-aware

Author: nitinjohnraj

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

@@ -1910,12 +1910,16 @@ multiclass VPseudoVIOT_M {
 multiclass VPseudoVCPR_V {
   foreach m = MxList in {
     defvar mx = m.MX;
-    defvar WriteVCompressV_MX = !cast<SchedWrite>("WriteVCompressV_" # mx);
-    defvar ReadVCompressV_MX = !cast<SchedRead>("ReadVCompressV_" # mx);
-
+    defvar sews = SchedSEWSet<mx>.val;
     let VLMul = m.value in
-      def _VM # "_" # m.MX : VPseudoUnaryAnyMask<m.vrclass, m.vrclass>,
-                             Sched<[WriteVCompressV_MX, ReadVCompressV_MX, ReadVCompressV_MX]>;
+      foreach e = sews in {
+        defvar suffix = "_" # m.MX # "_E" # e;
+        defvar WriteVCompressV_MX_E = !cast<SchedWrite>("WriteVCompressV" # suffix);
+        defvar ReadVCompressV_MX_E = !cast<SchedRead>("ReadVCompressV" # suffix);
+
+        def _VM # suffix : VPseudoUnaryAnyMask<m.vrclass, m.vrclass>,
+                           Sched<[WriteVCompressV_MX_E, ReadVCompressV_MX_E, ReadVCompressV_MX_E]>;
+      }
   }
 }
 
@@ -3860,6 +3864,28 @@ class VPatUnaryAnyMask<string intrinsic,
                    (mask_type VR:$rs2),
                    GPR:$vl, sew)>;
 
+class VPatUnaryAnyMask_E<string intrinsic,
+                         string inst,
+                         string kind,
+                         ValueType result_type,
+                         ValueType op1_type,
+                         ValueType mask_type,
+                         int log2sew,
+                         LMULInfo vlmul,
+                         int sew,
+                         VReg result_reg_class,
+                         VReg op1_reg_class> :
+  Pat<(result_type (!cast<Intrinsic>(intrinsic)
+                   (result_type result_reg_class:$merge),
+                   (op1_type op1_reg_class:$rs1),
+                   (mask_type VR:$rs2),
+                   VLOpFrag)),
+                   (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_E"#sew)
+                   (result_type result_reg_class:$merge),
+                   (op1_type op1_reg_class:$rs1),
+                   (mask_type VR:$rs2),
+                   GPR:$vl, log2sew)>;
+
 class VPatBinaryM<string intrinsic_name,
                   string inst,
                   ValueType result_type,
@@ -4172,6 +4198,16 @@ multiclass VPatUnaryV_V_AnyMask<string intrinsic, string instruction,
   }
 }
 
+multiclass VPatUnaryV_V_AnyMask_E<string intrinsic, string instruction,
+                                  list<VTypeInfo> vtilist> {
+  foreach vti = vtilist in {
+    def : VPatUnaryAnyMask_E<intrinsic, instruction, "VM",
+                           vti.Vector, vti.Vector, vti.Mask,
+                           vti.Log2SEW, vti.LMul, vti.SEW, vti.RegClass,
+                           vti.RegClass>;
+  }
+}
+
 multiclass VPatUnaryM_M<string intrinsic,
                          string inst>
 {
@@ -6434,11 +6470,11 @@ let Predicates = [HasVInstructionsAnyF] in {
 // 16.5. Vector Compress Instruction
 //===----------------------------------------------------------------------===//
 let Predicates = [HasVInstructions] in {
-  defm : VPatUnaryV_V_AnyMask<"int_riscv_vcompress", "PseudoVCOMPRESS", AllIntegerVectors>;
+  defm : VPatUnaryV_V_AnyMask_E<"int_riscv_vcompress", "PseudoVCOMPRESS", AllIntegerVectors>;
 } // Predicates = [HasVInstructions]
 
 let Predicates = [HasVInstructionsAnyF] in {
-  defm : VPatUnaryV_V_AnyMask<"int_riscv_vcompress", "PseudoVCOMPRESS", AllFloatVectors>;
+  defm : VPatUnaryV_V_AnyMask_E<"int_riscv_vcompress", "PseudoVCOMPRESS", AllFloatVectors>;
 } // Predicates = [HasVInstructionsAnyF]
 
 // Include the non-intrinsic ISel patterns

llvm/lib/Target/RISCV/RISCVScheduleV.td

@@ -54,6 +54,46 @@ multiclass LMULReadAdvanceImpl<string name, int val,
   }
 }
 
+// Define multiclasses to define SchedWrite, SchedRead,  WriteRes, and
+// ReadAdvance for each (name, LMUL, SEW) tuple for each LMUL in each of the
+// SchedMxList variants above.
+multiclass LMULSEWSchedWritesImpl<string name, list<string> MxList> {
+  foreach mx = MxList in {
+    if !eq(mx, "UpperBound") then
+      def name # "_" # mx : SchedWrite;
+    else
+      foreach sew = SchedSEWSet<mx>.val in
+        def name # "_" # mx # "_E" # sew : SchedWrite;
+  }
+}
+multiclass LMULSEWSchedReadsImpl<string name, list<string> MxList> {
+  foreach mx = MxList in {
+    if !eq(mx, "UpperBound") then
+      def name # "_" # mx : SchedRead;
+    else
+      foreach sew = SchedSEWSet<mx>.val in
+        def name # "_" # mx # "_E" # sew : SchedRead;
+  }
+}
+multiclass LMULSEWWriteResImpl<string name, list<ProcResourceKind> resources> {
+  foreach mx = SchedMxList in {
+    if !eq(mx, "UpperBound") then
+      def : WriteRes<!cast<SchedWrite>(name # "_" # mx), resources>;
+    else
+      foreach sew = SchedSEWSet<mx>.val in
+        def : WriteRes<!cast<SchedWrite>(name # "_" # mx # "_E" # sew), resources>;
+  }
+}
+multiclass LMULSEWReadAdvanceImpl<string name, int val,
+                                  list<SchedWrite> writes = []> {
+  foreach mx = SchedMxList in {
+    if !eq(mx, "UpperBound") then
+      def : ReadAdvance<!cast<SchedRead>(name # "_" # mx), val, writes>;
+    else
+      foreach sew = SchedSEWSet<mx>.val in
+        def : ReadAdvance<!cast<SchedRead>(name # "_" # mx # "_E" # sew), val, writes>;
+  }
+}
 // Define classes to define list containing all SchedWrites for each (name, LMUL)
 // pair for each LMUL in each of the SchedMxList variants above and name in
 // argument `names`. These classes can be used to construct a list of existing
@@ -78,6 +118,13 @@ multiclass LMULReadAdvance<string name, int val, list<SchedWrite> writes = []>
   : LMULReadAdvanceImpl<name, val, writes>;
 class LMULSchedWriteList<list<string> names> : LMULSchedWriteListImpl<names, SchedMxList>;
 
+multiclass LMULSEWSchedWrites<string name> : LMULSEWSchedWritesImpl<name, SchedMxList>;
+multiclass LMULSEWSchedReads<string name> : LMULSEWSchedReadsImpl<name, SchedMxList>;
+multiclass LMULSEWWriteRes<string name, list<ProcResourceKind> resources>
+  : LMULSEWWriteResImpl<name, resources>;
+multiclass LMULSEWReadAdvance<string name, int val, list<SchedWrite> writes = []>
+  : LMULSEWReadAdvanceImpl<name, val, writes>;
+
 multiclass LMULSchedWritesW<string name> : LMULSchedWritesImpl<name, SchedMxListW>;
 multiclass LMULSchedReadsW<string name> : LMULSchedReadsImpl<name, SchedMxListW>;
 multiclass LMULWriteResW<string name, list<ProcResourceKind> resources>
@@ -340,7 +387,7 @@ defm "" : LMULSchedWrites<"WriteVRGatherVV">;
 defm "" : LMULSchedWrites<"WriteVRGatherVX">;
 defm "" : LMULSchedWrites<"WriteVRGatherVI">;
 // 16.5. Vector Compress Instruction
-defm "" : LMULSchedWrites<"WriteVCompressV">;
+defm "" : LMULSEWSchedWrites<"WriteVCompressV">;
 // 16.6. Whole Vector Register Move
 // These are already LMUL aware
 def WriteVMov1V       : SchedWrite;
@@ -564,7 +611,7 @@ defm "" : LMULSchedReads<"ReadVRGatherVX_data">;
 defm "" : LMULSchedReads<"ReadVRGatherVX_index">;
 defm "" : LMULSchedReads<"ReadVRGatherVI_data">;
 // 16.5. Vector Compress Instruction
-defm "" : LMULSchedReads<"ReadVCompressV">;
+defm "" : LMULSEWSchedReads<"ReadVCompressV">;
 // 16.6. Whole Vector Register Move
 // These are already LMUL aware
 def ReadVMov1V        : SchedRead;
@@ -756,7 +803,7 @@ defm "" : LMULWriteRes<"WriteVFSlide1F", []>;
 defm "" : LMULWriteRes<"WriteVRGatherVV", []>;
 defm "" : LMULWriteRes<"WriteVRGatherVX", []>;
 defm "" : LMULWriteRes<"WriteVRGatherVI", []>;
-defm "" : LMULWriteRes<"WriteVCompressV", []>;
+defm "" : LMULSEWWriteRes<"WriteVCompressV", []>;
 // These are already LMUL aware
 def : WriteRes<WriteVMov1V, []>;
 def : WriteRes<WriteVMov2V, []>;
@@ -916,7 +963,9 @@ defm "" : LMULReadAdvance<"ReadVRGatherVV_index", 0>;
 defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>;
 defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>;
 defm "" : LMULReadAdvance<"ReadVRGatherVI_data", 0>;
-defm "" : LMULReadAdvance<"ReadVCompressV", 0>;
+defm "" : LMULReadAdvance<"ReadVGatherV", 0>;
+defm "" : LMULReadAdvance<"ReadVGatherX", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVCompressV", 0>;
 // These are already LMUL aware
 def : ReadAdvance<ReadVMov1V, 0>;
 def : ReadAdvance<ReadVMov2V, 0>;