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[RISCV] Use vmerge.vim for llvm.riscv.vfmerge with a 0.0 scalar operand.
We can use a 0 immediate to avoid needing to materialize 0 into an FPR first. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D94459
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‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3367,6 +3367,14 @@ defm "" : VPatBinaryV_VM<"int_riscv_vfmerge", "PseudoVMERGE",
33673367
defm "" : VPatBinaryV_XM<"int_riscv_vfmerge", "PseudoVFMERGE",
33683368
/*CarryOut = */0, /*vtilist=*/AllFloatVectors>;
33693369

3370+
foreach fvti = AllFloatVectors in {
3371+
defvar instr = !cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX);
3372+
def : Pat<(fvti.Vector (int_riscv_vfmerge (fvti.Vector fvti.RegClass:$rs2),
3373+
(fvti.Scalar (fpimm0)),
3374+
(fvti.Mask V0), (XLenVT GPR:$vl))),
3375+
(instr fvti.RegClass:$rs2, 0, (fvti.Mask V0), (NoX0 GPR:$vl), fvti.SEW)>;
3376+
}
3377+
33703378
//===----------------------------------------------------------------------===//
33713379
// 14.16. Vector Floating-Point Move Instruction
33723380
//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll

Lines changed: 154 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -439,3 +439,157 @@ entry:
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440440
ret <vscale x 16 x float> %a
441441
}
442+
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define <vscale x 1 x half> @intrinsic_vfmerge_vzm_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
444+
entry:
445+
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f16_nxv1f16_f16
446+
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
447+
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
448+
%a = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16(
449+
<vscale x 1 x half> %0,
450+
half zeroinitializer,
451+
<vscale x 1 x i1> %1,
452+
i32 %2)
453+
454+
ret <vscale x 1 x half> %a
455+
}
456+
457+
define <vscale x 2 x half> @intrinsic_vfmerge_vzm_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
458+
entry:
459+
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2f16_nxv2f16_f16
460+
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
461+
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
462+
%a = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16(
463+
<vscale x 2 x half> %0,
464+
half zeroinitializer,
465+
<vscale x 2 x i1> %1,
466+
i32 %2)
467+
468+
ret <vscale x 2 x half> %a
469+
}
470+
471+
define <vscale x 4 x half> @intrinsic_vfmerge_vzm_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
472+
entry:
473+
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4f16_nxv4f16_f16
474+
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
475+
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
476+
%a = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16(
477+
<vscale x 4 x half> %0,
478+
half zeroinitializer,
479+
<vscale x 4 x i1> %1,
480+
i32 %2)
481+
482+
ret <vscale x 4 x half> %a
483+
}
484+
485+
define <vscale x 8 x half> @intrinsic_vfmerge_vzm_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
486+
entry:
487+
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8f16_nxv8f16_f16
488+
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
489+
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
490+
%a = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16(
491+
<vscale x 8 x half> %0,
492+
half zeroinitializer,
493+
<vscale x 8 x i1> %1,
494+
i32 %2)
495+
496+
ret <vscale x 8 x half> %a
497+
}
498+
499+
define <vscale x 16 x half> @intrinsic_vfmerge_vzm_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
500+
entry:
501+
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv16f16_nxv16f16_f16
502+
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
503+
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
504+
%a = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16(
505+
<vscale x 16 x half> %0,
506+
half zeroinitializer,
507+
<vscale x 16 x i1> %1,
508+
i32 %2)
509+
510+
ret <vscale x 16 x half> %a
511+
}
512+
513+
define <vscale x 32 x half> @intrinsic_vfmerge_vzm_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, <vscale x 32 x i1> %1, i32 %2) nounwind {
514+
entry:
515+
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv32f16_nxv32f16_f16
516+
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
517+
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
518+
%a = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16(
519+
<vscale x 32 x half> %0,
520+
half zeroinitializer,
521+
<vscale x 32 x i1> %1,
522+
i32 %2)
523+
524+
ret <vscale x 32 x half> %a
525+
}
526+
527+
define <vscale x 1 x float> @intrinsic_vfmerge_vzm_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
528+
entry:
529+
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f32_nxv1f32_f32
530+
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
531+
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
532+
%a = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32(
533+
<vscale x 1 x float> %0,
534+
float zeroinitializer,
535+
<vscale x 1 x i1> %1,
536+
i32 %2)
537+
538+
ret <vscale x 1 x float> %a
539+
}
540+
541+
define <vscale x 2 x float> @intrinsic_vfmerge_vzm_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
542+
entry:
543+
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2f32_nxv2f32_f32
544+
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
545+
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
546+
%a = call <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32(
547+
<vscale x 2 x float> %0,
548+
float zeroinitializer,
549+
<vscale x 2 x i1> %1,
550+
i32 %2)
551+
552+
ret <vscale x 2 x float> %a
553+
}
554+
555+
define <vscale x 4 x float> @intrinsic_vfmerge_vzm_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
556+
entry:
557+
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4f32_nxv4f32_f32
558+
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
559+
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
560+
%a = call <vscale x 4 x float> @llvm.riscv.vfmerge.nxv4f32.f32(
561+
<vscale x 4 x float> %0,
562+
float zeroinitializer,
563+
<vscale x 4 x i1> %1,
564+
i32 %2)
565+
566+
ret <vscale x 4 x float> %a
567+
}
568+
569+
define <vscale x 8 x float> @intrinsic_vfmerge_vzm_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
570+
entry:
571+
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8f32_nxv8f32_f32
572+
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
573+
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
574+
%a = call <vscale x 8 x float> @llvm.riscv.vfmerge.nxv8f32.f32(
575+
<vscale x 8 x float> %0,
576+
float zeroinitializer,
577+
<vscale x 8 x i1> %1,
578+
i32 %2)
579+
580+
ret <vscale x 8 x float> %a
581+
}
582+
583+
define <vscale x 16 x float> @intrinsic_vfmerge_vzm_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
584+
entry:
585+
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv16f32_nxv16f32_f32
586+
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
587+
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
588+
%a = call <vscale x 16 x float> @llvm.riscv.vfmerge.nxv16f32.f32(
589+
<vscale x 16 x float> %0,
590+
float zeroinitializer,
591+
<vscale x 16 x i1> %1,
592+
i32 %2)
593+
594+
ret <vscale x 16 x float> %a
595+
}

‎llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll

Lines changed: 210 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -599,3 +599,213 @@ entry:
599599

600600
ret <vscale x 8 x double> %a
601601
}
602+
603+
define <vscale x 1 x half> @intrinsic_vfmerge_vzm_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
604+
entry:
605+
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f16_nxv1f16_f16
606+
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
607+
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
608+
%a = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16(
609+
<vscale x 1 x half> %0,
610+
half zeroinitializer,
611+
<vscale x 1 x i1> %1,
612+
i64 %2)
613+
614+
ret <vscale x 1 x half> %a
615+
}
616+
617+
define <vscale x 2 x half> @intrinsic_vfmerge_vzm_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
618+
entry:
619+
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2f16_nxv2f16_f16
620+
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
621+
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
622+
%a = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16(
623+
<vscale x 2 x half> %0,
624+
half zeroinitializer,
625+
<vscale x 2 x i1> %1,
626+
i64 %2)
627+
628+
ret <vscale x 2 x half> %a
629+
}
630+
631+
define <vscale x 4 x half> @intrinsic_vfmerge_vzm_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
632+
entry:
633+
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4f16_nxv4f16_f16
634+
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
635+
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
636+
%a = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16(
637+
<vscale x 4 x half> %0,
638+
half zeroinitializer,
639+
<vscale x 4 x i1> %1,
640+
i64 %2)
641+
642+
ret <vscale x 4 x half> %a
643+
}
644+
645+
define <vscale x 8 x half> @intrinsic_vfmerge_vzm_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
646+
entry:
647+
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8f16_nxv8f16_f16
648+
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
649+
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
650+
%a = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16(
651+
<vscale x 8 x half> %0,
652+
half zeroinitializer,
653+
<vscale x 8 x i1> %1,
654+
i64 %2)
655+
656+
ret <vscale x 8 x half> %a
657+
}
658+
659+
define <vscale x 16 x half> @intrinsic_vfmerge_vzm_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
660+
entry:
661+
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv16f16_nxv16f16_f16
662+
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
663+
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
664+
%a = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16(
665+
<vscale x 16 x half> %0,
666+
half zeroinitializer,
667+
<vscale x 16 x i1> %1,
668+
i64 %2)
669+
670+
ret <vscale x 16 x half> %a
671+
}
672+
673+
define <vscale x 32 x half> @intrinsic_vfmerge_vzm_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
674+
entry:
675+
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv32f16_nxv32f16_f16
676+
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
677+
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
678+
%a = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16(
679+
<vscale x 32 x half> %0,
680+
half zeroinitializer,
681+
<vscale x 32 x i1> %1,
682+
i64 %2)
683+
684+
ret <vscale x 32 x half> %a
685+
}
686+
687+
define <vscale x 1 x float> @intrinsic_vfmerge_vzm_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
688+
entry:
689+
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f32_nxv1f32_f32
690+
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
691+
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
692+
%a = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32(
693+
<vscale x 1 x float> %0,
694+
float zeroinitializer,
695+
<vscale x 1 x i1> %1,
696+
i64 %2)
697+
698+
ret <vscale x 1 x float> %a
699+
}
700+
701+
define <vscale x 2 x float> @intrinsic_vfmerge_vzm_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
702+
entry:
703+
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2f32_nxv2f32_f32
704+
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
705+
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
706+
%a = call <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32(
707+
<vscale x 2 x float> %0,
708+
float zeroinitializer,
709+
<vscale x 2 x i1> %1,
710+
i64 %2)
711+
712+
ret <vscale x 2 x float> %a
713+
}
714+
715+
define <vscale x 4 x float> @intrinsic_vfmerge_vzm_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
716+
entry:
717+
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4f32_nxv4f32_f32
718+
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
719+
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
720+
%a = call <vscale x 4 x float> @llvm.riscv.vfmerge.nxv4f32.f32(
721+
<vscale x 4 x float> %0,
722+
float zeroinitializer,
723+
<vscale x 4 x i1> %1,
724+
i64 %2)
725+
726+
ret <vscale x 4 x float> %a
727+
}
728+
729+
define <vscale x 8 x float> @intrinsic_vfmerge_vzm_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
730+
entry:
731+
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8f32_nxv8f32_f32
732+
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
733+
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
734+
%a = call <vscale x 8 x float> @llvm.riscv.vfmerge.nxv8f32.f32(
735+
<vscale x 8 x float> %0,
736+
float zeroinitializer,
737+
<vscale x 8 x i1> %1,
738+
i64 %2)
739+
740+
ret <vscale x 8 x float> %a
741+
}
742+
743+
define <vscale x 16 x float> @intrinsic_vfmerge_vzm_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
744+
entry:
745+
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv16f32_nxv16f32_f32
746+
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
747+
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
748+
%a = call <vscale x 16 x float> @llvm.riscv.vfmerge.nxv16f32.f32(
749+
<vscale x 16 x float> %0,
750+
float zeroinitializer,
751+
<vscale x 16 x i1> %1,
752+
i64 %2)
753+
754+
ret <vscale x 16 x float> %a
755+
}
756+
757+
define <vscale x 1 x double> @intrinsic_vfmerge_vzm_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
758+
entry:
759+
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f64_nxv1f64_f64
760+
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
761+
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
762+
%a = call <vscale x 1 x double> @llvm.riscv.vfmerge.nxv1f64.f64(
763+
<vscale x 1 x double> %0,
764+
double zeroinitializer,
765+
<vscale x 1 x i1> %1,
766+
i64 %2)
767+
768+
ret <vscale x 1 x double> %a
769+
}
770+
771+
define <vscale x 2 x double> @intrinsic_vfmerge_vzm_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
772+
entry:
773+
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2f64_nxv2f64_f64
774+
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
775+
; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
776+
%a = call <vscale x 2 x double> @llvm.riscv.vfmerge.nxv2f64.f64(
777+
<vscale x 2 x double> %0,
778+
double zeroinitializer,
779+
<vscale x 2 x i1> %1,
780+
i64 %2)
781+
782+
ret <vscale x 2 x double> %a
783+
}
784+
785+
define <vscale x 4 x double> @intrinsic_vfmerge_vzm_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
786+
entry:
787+
; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4f64_nxv4f64_f64
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
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; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
790+
%a = call <vscale x 4 x double> @llvm.riscv.vfmerge.nxv4f64.f64(
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<vscale x 4 x double> %0,
792+
double zeroinitializer,
793+
<vscale x 4 x i1> %1,
794+
i64 %2)
795+
796+
ret <vscale x 4 x double> %a
797+
}
798+
799+
define <vscale x 8 x double> @intrinsic_vfmerge_vzm_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
800+
entry:
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; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8f64_nxv8f64_f64
802+
; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
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; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
804+
%a = call <vscale x 8 x double> @llvm.riscv.vfmerge.nxv8f64.f64(
805+
<vscale x 8 x double> %0,
806+
double zeroinitializer,
807+
<vscale x 8 x i1> %1,
808+
i64 %2)
809+
810+
ret <vscale x 8 x double> %a
811+
}

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