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[NFC] Update test/CodeGen/RISCV/select-constant-xor.ll to use RV --check-prefix
This is only for consistency with test cases. Differential Revision: https://reviews.llvm.org/D112364
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‎llvm/test/CodeGen/RISCV/select-constant-xor.ll

Lines changed: 155 additions & 155 deletions
Original file line numberDiff line numberDiff line change
@@ -1,87 +1,87 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 %s -o - | FileCheck %s --check-prefix=CHECK32
3-
; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s --check-prefix=CHECK64
2+
; RUN: llc -mtriple=riscv32 %s -o - | FileCheck %s --check-prefix=RV32
3+
; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s --check-prefix=RV64
44

55
define i32 @xori64i32(i64 %a) {
6-
; CHECK32-LABEL: xori64i32:
7-
; CHECK32: # %bb.0:
8-
; CHECK32-NEXT: srai a0, a1, 31
9-
; CHECK32-NEXT: lui a1, 524288
10-
; CHECK32-NEXT: addi a1, a1, -1
11-
; CHECK32-NEXT: xor a0, a0, a1
12-
; CHECK32-NEXT: ret
6+
; RV32-LABEL: xori64i32:
7+
; RV32: # %bb.0:
8+
; RV32-NEXT: srai a0, a1, 31
9+
; RV32-NEXT: lui a1, 524288
10+
; RV32-NEXT: addi a1, a1, -1
11+
; RV32-NEXT: xor a0, a0, a1
12+
; RV32-NEXT: ret
1313
;
14-
; CHECK64-LABEL: xori64i32:
15-
; CHECK64: # %bb.0:
16-
; CHECK64-NEXT: srai a0, a0, 63
17-
; CHECK64-NEXT: lui a1, 524288
18-
; CHECK64-NEXT: addiw a1, a1, -1
19-
; CHECK64-NEXT: xor a0, a0, a1
20-
; CHECK64-NEXT: ret
14+
; RV64-LABEL: xori64i32:
15+
; RV64: # %bb.0:
16+
; RV64-NEXT: srai a0, a0, 63
17+
; RV64-NEXT: lui a1, 524288
18+
; RV64-NEXT: addiw a1, a1, -1
19+
; RV64-NEXT: xor a0, a0, a1
20+
; RV64-NEXT: ret
2121
%shr4 = ashr i64 %a, 63
2222
%conv5 = trunc i64 %shr4 to i32
2323
%xor = xor i32 %conv5, 2147483647
2424
ret i32 %xor
2525
}
2626

2727
define i64 @selecti64i64(i64 %a) {
28-
; CHECK32-LABEL: selecti64i64:
29-
; CHECK32: # %bb.0:
30-
; CHECK32-NEXT: srai a1, a1, 31
31-
; CHECK32-NEXT: lui a0, 524288
32-
; CHECK32-NEXT: addi a0, a0, -1
33-
; CHECK32-NEXT: xor a0, a1, a0
34-
; CHECK32-NEXT: ret
28+
; RV32-LABEL: selecti64i64:
29+
; RV32: # %bb.0:
30+
; RV32-NEXT: srai a1, a1, 31
31+
; RV32-NEXT: lui a0, 524288
32+
; RV32-NEXT: addi a0, a0, -1
33+
; RV32-NEXT: xor a0, a1, a0
34+
; RV32-NEXT: ret
3535
;
36-
; CHECK64-LABEL: selecti64i64:
37-
; CHECK64: # %bb.0:
38-
; CHECK64-NEXT: srai a0, a0, 63
39-
; CHECK64-NEXT: lui a1, 524288
40-
; CHECK64-NEXT: addiw a1, a1, -1
41-
; CHECK64-NEXT: xor a0, a0, a1
42-
; CHECK64-NEXT: ret
36+
; RV64-LABEL: selecti64i64:
37+
; RV64: # %bb.0:
38+
; RV64-NEXT: srai a0, a0, 63
39+
; RV64-NEXT: lui a1, 524288
40+
; RV64-NEXT: addiw a1, a1, -1
41+
; RV64-NEXT: xor a0, a0, a1
42+
; RV64-NEXT: ret
4343
%c = icmp sgt i64 %a, -1
4444
%s = select i1 %c, i64 2147483647, i64 -2147483648
4545
ret i64 %s
4646
}
4747

4848
define i32 @selecti64i32(i64 %a) {
49-
; CHECK32-LABEL: selecti64i32:
50-
; CHECK32: # %bb.0:
51-
; CHECK32-NEXT: addi a0, zero, -1
52-
; CHECK32-NEXT: slt a0, a0, a1
53-
; CHECK32-NEXT: lui a1, 524288
54-
; CHECK32-NEXT: sub a0, a1, a0
55-
; CHECK32-NEXT: ret
49+
; RV32-LABEL: selecti64i32:
50+
; RV32: # %bb.0:
51+
; RV32-NEXT: addi a0, zero, -1
52+
; RV32-NEXT: slt a0, a0, a1
53+
; RV32-NEXT: lui a1, 524288
54+
; RV32-NEXT: sub a0, a1, a0
55+
; RV32-NEXT: ret
5656
;
57-
; CHECK64-LABEL: selecti64i32:
58-
; CHECK64: # %bb.0:
59-
; CHECK64-NEXT: srai a0, a0, 63
60-
; CHECK64-NEXT: lui a1, 524288
61-
; CHECK64-NEXT: addiw a1, a1, -1
62-
; CHECK64-NEXT: xor a0, a0, a1
63-
; CHECK64-NEXT: ret
57+
; RV64-LABEL: selecti64i32:
58+
; RV64: # %bb.0:
59+
; RV64-NEXT: srai a0, a0, 63
60+
; RV64-NEXT: lui a1, 524288
61+
; RV64-NEXT: addiw a1, a1, -1
62+
; RV64-NEXT: xor a0, a0, a1
63+
; RV64-NEXT: ret
6464
%c = icmp sgt i64 %a, -1
6565
%s = select i1 %c, i32 2147483647, i32 -2147483648
6666
ret i32 %s
6767
}
6868

6969
define i64 @selecti32i64(i32 %a) {
70-
; CHECK32-LABEL: selecti32i64:
71-
; CHECK32: # %bb.0:
72-
; CHECK32-NEXT: srai a1, a0, 31
73-
; CHECK32-NEXT: lui a0, 524288
74-
; CHECK32-NEXT: addi a0, a0, -1
75-
; CHECK32-NEXT: xor a0, a1, a0
76-
; CHECK32-NEXT: ret
70+
; RV32-LABEL: selecti32i64:
71+
; RV32: # %bb.0:
72+
; RV32-NEXT: srai a1, a0, 31
73+
; RV32-NEXT: lui a0, 524288
74+
; RV32-NEXT: addi a0, a0, -1
75+
; RV32-NEXT: xor a0, a1, a0
76+
; RV32-NEXT: ret
7777
;
78-
; CHECK64-LABEL: selecti32i64:
79-
; CHECK64: # %bb.0:
80-
; CHECK64-NEXT: sraiw a0, a0, 31
81-
; CHECK64-NEXT: lui a1, 524288
82-
; CHECK64-NEXT: addiw a1, a1, -1
83-
; CHECK64-NEXT: xor a0, a0, a1
84-
; CHECK64-NEXT: ret
78+
; RV64-LABEL: selecti32i64:
79+
; RV64: # %bb.0:
80+
; RV64-NEXT: sraiw a0, a0, 31
81+
; RV64-NEXT: lui a1, 524288
82+
; RV64-NEXT: addiw a1, a1, -1
83+
; RV64-NEXT: xor a0, a0, a1
84+
; RV64-NEXT: ret
8585
%c = icmp sgt i32 %a, -1
8686
%s = select i1 %c, i64 2147483647, i64 -2147483648
8787
ret i64 %s
@@ -90,149 +90,149 @@ define i64 @selecti32i64(i32 %a) {
9090

9191

9292
define i8 @xori32i8(i32 %a) {
93-
; CHECK32-LABEL: xori32i8:
94-
; CHECK32: # %bb.0:
95-
; CHECK32-NEXT: srai a0, a0, 31
96-
; CHECK32-NEXT: xori a0, a0, 84
97-
; CHECK32-NEXT: ret
93+
; RV32-LABEL: xori32i8:
94+
; RV32: # %bb.0:
95+
; RV32-NEXT: srai a0, a0, 31
96+
; RV32-NEXT: xori a0, a0, 84
97+
; RV32-NEXT: ret
9898
;
99-
; CHECK64-LABEL: xori32i8:
100-
; CHECK64: # %bb.0:
101-
; CHECK64-NEXT: sraiw a0, a0, 31
102-
; CHECK64-NEXT: xori a0, a0, 84
103-
; CHECK64-NEXT: ret
99+
; RV64-LABEL: xori32i8:
100+
; RV64: # %bb.0:
101+
; RV64-NEXT: sraiw a0, a0, 31
102+
; RV64-NEXT: xori a0, a0, 84
103+
; RV64-NEXT: ret
104104
%shr4 = ashr i32 %a, 31
105105
%conv5 = trunc i32 %shr4 to i8
106106
%xor = xor i8 %conv5, 84
107107
ret i8 %xor
108108
}
109109

110110
define i32 @selecti32i32(i32 %a) {
111-
; CHECK32-LABEL: selecti32i32:
112-
; CHECK32: # %bb.0:
113-
; CHECK32-NEXT: srai a0, a0, 31
114-
; CHECK32-NEXT: xori a0, a0, 84
115-
; CHECK32-NEXT: ret
111+
; RV32-LABEL: selecti32i32:
112+
; RV32: # %bb.0:
113+
; RV32-NEXT: srai a0, a0, 31
114+
; RV32-NEXT: xori a0, a0, 84
115+
; RV32-NEXT: ret
116116
;
117-
; CHECK64-LABEL: selecti32i32:
118-
; CHECK64: # %bb.0:
119-
; CHECK64-NEXT: sraiw a0, a0, 31
120-
; CHECK64-NEXT: xori a0, a0, 84
121-
; CHECK64-NEXT: ret
117+
; RV64-LABEL: selecti32i32:
118+
; RV64: # %bb.0:
119+
; RV64-NEXT: sraiw a0, a0, 31
120+
; RV64-NEXT: xori a0, a0, 84
121+
; RV64-NEXT: ret
122122
%c = icmp sgt i32 %a, -1
123123
%s = select i1 %c, i32 84, i32 -85
124124
ret i32 %s
125125
}
126126

127127
define i8 @selecti32i8(i32 %a) {
128-
; CHECK32-LABEL: selecti32i8:
129-
; CHECK32: # %bb.0:
130-
; CHECK32-NEXT: srai a0, a0, 31
131-
; CHECK32-NEXT: xori a0, a0, 84
132-
; CHECK32-NEXT: ret
128+
; RV32-LABEL: selecti32i8:
129+
; RV32: # %bb.0:
130+
; RV32-NEXT: srai a0, a0, 31
131+
; RV32-NEXT: xori a0, a0, 84
132+
; RV32-NEXT: ret
133133
;
134-
; CHECK64-LABEL: selecti32i8:
135-
; CHECK64: # %bb.0:
136-
; CHECK64-NEXT: sraiw a0, a0, 31
137-
; CHECK64-NEXT: xori a0, a0, 84
138-
; CHECK64-NEXT: ret
134+
; RV64-LABEL: selecti32i8:
135+
; RV64: # %bb.0:
136+
; RV64-NEXT: sraiw a0, a0, 31
137+
; RV64-NEXT: xori a0, a0, 84
138+
; RV64-NEXT: ret
139139
%c = icmp sgt i32 %a, -1
140140
%s = select i1 %c, i8 84, i8 -85
141141
ret i8 %s
142142
}
143143

144144
define i32 @selecti8i32(i8 %a) {
145-
; CHECK32-LABEL: selecti8i32:
146-
; CHECK32: # %bb.0:
147-
; CHECK32-NEXT: slli a0, a0, 24
148-
; CHECK32-NEXT: srai a0, a0, 31
149-
; CHECK32-NEXT: xori a0, a0, 84
150-
; CHECK32-NEXT: ret
145+
; RV32-LABEL: selecti8i32:
146+
; RV32: # %bb.0:
147+
; RV32-NEXT: slli a0, a0, 24
148+
; RV32-NEXT: srai a0, a0, 31
149+
; RV32-NEXT: xori a0, a0, 84
150+
; RV32-NEXT: ret
151151
;
152-
; CHECK64-LABEL: selecti8i32:
153-
; CHECK64: # %bb.0:
154-
; CHECK64-NEXT: slli a0, a0, 56
155-
; CHECK64-NEXT: srai a0, a0, 63
156-
; CHECK64-NEXT: xori a0, a0, 84
157-
; CHECK64-NEXT: ret
152+
; RV64-LABEL: selecti8i32:
153+
; RV64: # %bb.0:
154+
; RV64-NEXT: slli a0, a0, 56
155+
; RV64-NEXT: srai a0, a0, 63
156+
; RV64-NEXT: xori a0, a0, 84
157+
; RV64-NEXT: ret
158158
%c = icmp sgt i8 %a, -1
159159
%s = select i1 %c, i32 84, i32 -85
160160
ret i32 %s
161161
}
162162

163163
define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {
164-
; CHECK32-LABEL: icmpasreq:
165-
; CHECK32: # %bb.0:
166-
; CHECK32-NEXT: bltz a0, .LBB8_2
167-
; CHECK32-NEXT: # %bb.1:
168-
; CHECK32-NEXT: mv a1, a2
169-
; CHECK32-NEXT: .LBB8_2:
170-
; CHECK32-NEXT: mv a0, a1
171-
; CHECK32-NEXT: ret
164+
; RV32-LABEL: icmpasreq:
165+
; RV32: # %bb.0:
166+
; RV32-NEXT: bltz a0, .LBB8_2
167+
; RV32-NEXT: # %bb.1:
168+
; RV32-NEXT: mv a1, a2
169+
; RV32-NEXT: .LBB8_2:
170+
; RV32-NEXT: mv a0, a1
171+
; RV32-NEXT: ret
172172
;
173-
; CHECK64-LABEL: icmpasreq:
174-
; CHECK64: # %bb.0:
175-
; CHECK64-NEXT: sext.w a3, a0
176-
; CHECK64-NEXT: mv a0, a1
177-
; CHECK64-NEXT: bltz a3, .LBB8_2
178-
; CHECK64-NEXT: # %bb.1:
179-
; CHECK64-NEXT: mv a0, a2
180-
; CHECK64-NEXT: .LBB8_2:
181-
; CHECK64-NEXT: ret
173+
; RV64-LABEL: icmpasreq:
174+
; RV64: # %bb.0:
175+
; RV64-NEXT: sext.w a3, a0
176+
; RV64-NEXT: mv a0, a1
177+
; RV64-NEXT: bltz a3, .LBB8_2
178+
; RV64-NEXT: # %bb.1:
179+
; RV64-NEXT: mv a0, a2
180+
; RV64-NEXT: .LBB8_2:
181+
; RV64-NEXT: ret
182182
%sh = ashr i32 %input, 31
183183
%c = icmp eq i32 %sh, -1
184184
%s = select i1 %c, i32 %a, i32 %b
185185
ret i32 %s
186186
}
187187

188188
define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
189-
; CHECK32-LABEL: icmpasrne:
190-
; CHECK32: # %bb.0:
191-
; CHECK32-NEXT: bgez a0, .LBB9_2
192-
; CHECK32-NEXT: # %bb.1:
193-
; CHECK32-NEXT: mv a1, a2
194-
; CHECK32-NEXT: .LBB9_2:
195-
; CHECK32-NEXT: mv a0, a1
196-
; CHECK32-NEXT: ret
189+
; RV32-LABEL: icmpasrne:
190+
; RV32: # %bb.0:
191+
; RV32-NEXT: bgez a0, .LBB9_2
192+
; RV32-NEXT: # %bb.1:
193+
; RV32-NEXT: mv a1, a2
194+
; RV32-NEXT: .LBB9_2:
195+
; RV32-NEXT: mv a0, a1
196+
; RV32-NEXT: ret
197197
;
198-
; CHECK64-LABEL: icmpasrne:
199-
; CHECK64: # %bb.0:
200-
; CHECK64-NEXT: sext.w a3, a0
201-
; CHECK64-NEXT: mv a0, a1
202-
; CHECK64-NEXT: bgez a3, .LBB9_2
203-
; CHECK64-NEXT: # %bb.1:
204-
; CHECK64-NEXT: mv a0, a2
205-
; CHECK64-NEXT: .LBB9_2:
206-
; CHECK64-NEXT: ret
198+
; RV64-LABEL: icmpasrne:
199+
; RV64: # %bb.0:
200+
; RV64-NEXT: sext.w a3, a0
201+
; RV64-NEXT: mv a0, a1
202+
; RV64-NEXT: bgez a3, .LBB9_2
203+
; RV64-NEXT: # %bb.1:
204+
; RV64-NEXT: mv a0, a2
205+
; RV64-NEXT: .LBB9_2:
206+
; RV64-NEXT: ret
207207
%sh = ashr i32 %input, 31
208208
%c = icmp ne i32 %sh, -1
209209
%s = select i1 %c, i32 %a, i32 %b
210210
ret i32 %s
211211
}
212212

213213
define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
214-
; CHECK32-LABEL: oneusecmp:
215-
; CHECK32: # %bb.0:
216-
; CHECK32-NEXT: srai a3, a0, 31
217-
; CHECK32-NEXT: xori a3, a3, 127
218-
; CHECK32-NEXT: bltz a0, .LBB10_2
219-
; CHECK32-NEXT: # %bb.1:
220-
; CHECK32-NEXT: mv a2, a1
221-
; CHECK32-NEXT: .LBB10_2:
222-
; CHECK32-NEXT: add a0, a3, a2
223-
; CHECK32-NEXT: ret
214+
; RV32-LABEL: oneusecmp:
215+
; RV32: # %bb.0:
216+
; RV32-NEXT: srai a3, a0, 31
217+
; RV32-NEXT: xori a3, a3, 127
218+
; RV32-NEXT: bltz a0, .LBB10_2
219+
; RV32-NEXT: # %bb.1:
220+
; RV32-NEXT: mv a2, a1
221+
; RV32-NEXT: .LBB10_2:
222+
; RV32-NEXT: add a0, a3, a2
223+
; RV32-NEXT: ret
224224
;
225-
; CHECK64-LABEL: oneusecmp:
226-
; CHECK64: # %bb.0:
227-
; CHECK64-NEXT: sext.w a3, a0
228-
; CHECK64-NEXT: srli a0, a3, 31
229-
; CHECK64-NEXT: xori a0, a0, 127
230-
; CHECK64-NEXT: bltz a3, .LBB10_2
231-
; CHECK64-NEXT: # %bb.1:
232-
; CHECK64-NEXT: mv a2, a1
233-
; CHECK64-NEXT: .LBB10_2:
234-
; CHECK64-NEXT: addw a0, a0, a2
235-
; CHECK64-NEXT: ret
225+
; RV64-LABEL: oneusecmp:
226+
; RV64: # %bb.0:
227+
; RV64-NEXT: sext.w a3, a0
228+
; RV64-NEXT: srli a0, a3, 31
229+
; RV64-NEXT: xori a0, a0, 127
230+
; RV64-NEXT: bltz a3, .LBB10_2
231+
; RV64-NEXT: # %bb.1:
232+
; RV64-NEXT: mv a2, a1
233+
; RV64-NEXT: .LBB10_2:
234+
; RV64-NEXT: addw a0, a0, a2
235+
; RV64-NEXT: ret
236236
%c = icmp sle i32 %a, -1
237237
%s = select i1 %c, i32 -128, i32 127
238238
%s2 = select i1 %c, i32 %d, i32 %b

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