@@ -144,3 +144,142 @@ defm VSTU2D : VSTm<"vstu2d", 0xd2, V64>;
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// Section 8.9.12 - VSTL2D (Vector Store Lower 2D)
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defm VSTL2D : VSTm<"vstl2d", 0xd3, V64>;
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+
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+ // Multiclass for VGT instructions
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+ let mayLoad = 1, hasSideEffects = 0, Uses = [VL] in
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+ multiclass VGTbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
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+ dag dag_in, string disEnc = ""> {
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+ let DisableEncoding = disEnc in
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+ def "" : RVM<opc, (outs RC:$vx), dag_in,
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+ !strconcat(opcStr, " $vx, ", argStr)>;
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+ let Constraints = "$vx = $base", DisableEncoding = disEnc#"$base",
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+ isCodeGenOnly = 1 in
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+ def _v : RVM<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
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+ !strconcat(opcStr, " $vx, ", argStr)>;
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+ }
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+ multiclass VGTlm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
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+ dag dag_in> {
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+ defm "" : VGTbm<opcStr, argStr, opc, RC, dag_in>;
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+ let isCodeGenOnly = 1, VE_VLInUse = 1 in {
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+ defm l : VGTbm<opcStr, argStr, opc, RC, !con(dag_in, (ins I32:$vl)),
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+ "$vl,">;
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+ defm L : VGTbm<opcStr, argStr, opc, RC, !con(dag_in, (ins VLS:$vl)),
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+ "$vl,">;
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+ }
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+ }
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+ multiclass VGTmm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
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+ dag dag_in> {
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+ defm "" : VGTlm<opcStr, argStr, opc, RC, dag_in>;
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+ let m = ?, VE_VLWithMask = 1 in
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+ defm m : VGTlm<opcStr, argStr#", $m", opc, RC, !con(dag_in, (ins VM:$m))>;
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+ }
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+ let VE_VLIndex = 4 in
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+ multiclass VGTlhm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
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+ dag dag_in> {
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+ defm rr : VGTmm<opcStr, argStr#", $sy, $sz", opc, RC,
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+ !con(dag_in, (ins I64:$sy, I64:$sz))>;
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+ let cy = 0 in
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+ defm ir : VGTmm<opcStr, argStr#", $sy, $sz", opc, RC,
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+ !con(dag_in, (ins simm7:$sy, I64:$sz))>;
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+ let cz = 0 in
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+ defm rz : VGTmm<opcStr, argStr#", $sy, $sz", opc, RC,
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+ !con(dag_in, (ins I64:$sy, zero:$sz))>;
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+ let cy = 0, cz = 0 in
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+ defm iz : VGTmm<opcStr, argStr#", $sy, $sz", opc, RC,
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+ !con(dag_in, (ins simm7:$sy, zero:$sz))>;
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+ }
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+ multiclass VGTtgm<string opcStr, bits<8>opc, RegisterClass RC> {
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+ let vy = ? in defm v : VGTlhm<opcStr, "$vy", opc, RC, (ins V64:$vy)>;
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+ let cs = 1, sw = ? in defm s : VGTlhm<opcStr, "$sw", opc, RC, (ins I64:$sw)>;
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+ }
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+ multiclass VGTm<string opcStr, bits<8>opc, RegisterClass RC> {
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+ let vc = 1 in defm "" : VGTtgm<opcStr, opc, RC>;
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+ let vc = 0 in defm NC : VGTtgm<opcStr#".nc", opc, RC>;
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+ }
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+
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+ // Section 8.9.13 - VGT (Vector Gather)
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+ defm VGT : VGTm<"vgt", 0xa1, V64>;
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+
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+ // Section 8.9.14 - VGTU (Vector Gather Upper)
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+ defm VGTU : VGTm<"vgtu", 0xa2, V64>;
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+
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+ // Section 8.9.15 - VGTL (Vector Gather Lower)
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+ defm VGTLSX : VGTm<"vgtl.sx", 0xa3, V64>;
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+ let cx = 1 in defm VGTLZX : VGTm<"vgtl.zx", 0xa3, V64>;
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+ def : MnemonicAlias<"vgtl", "vgtl.zx">;
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+ def : MnemonicAlias<"vgtl.nc", "vgtl.zx.nc">;
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+
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+ // Multiclass for VSC instructions
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+ let mayStore = 1, hasSideEffects = 0, Uses = [VL] in
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+ multiclass VSCbm<string opcStr, string argStr, bits<8>opc, dag dag_in> {
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+ def "" : RVM<opc, (outs), dag_in, !strconcat(opcStr, argStr)>;
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+ let DisableEncoding = "$vl", isCodeGenOnly = 1, VE_VLInUse = 1 in {
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+ def l : RVM<opc, (outs), !con(dag_in, (ins I32:$vl)),
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+ !strconcat(opcStr, argStr)>;
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+ def L : RVM<opc, (outs), !con(dag_in, (ins VLS:$vl)),
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+ !strconcat(opcStr, argStr)>;
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+ }
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+ }
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+ multiclass VSCmm<string opcStr, string argStr, bits<8>opc, dag dag_in> {
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+ defm "" : VSCbm<opcStr, argStr, opc, dag_in>;
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+ let m = ?, VE_VLWithMask = 1 in
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+ defm m : VSCbm<opcStr, argStr#", $m", opc, !con(dag_in, (ins VM:$m))>;
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+ }
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+ let VE_VLIndex = 4 in
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+ multiclass VSClhm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
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+ dag dag_in> {
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+ defm rrv : VSCmm<opcStr, " $vx, "#argStr#", $sy, $sz", opc,
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+ !con(dag_in, (ins I64:$sy, I64:$sz, RC:$vx))>;
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+ let cy = 0 in
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+ defm irv : VSCmm<opcStr, " $vx, "#argStr#", $sy, $sz", opc,
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+ !con(dag_in, (ins simm7:$sy, I64:$sz, RC:$vx))>;
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+ let cz = 0 in
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+ defm rzv : VSCmm<opcStr, " $vx, "#argStr#", $sy, $sz", opc,
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+ !con(dag_in, (ins I64:$sy, zero:$sz, RC:$vx))>;
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+ let cy = 0, cz = 0 in
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+ defm izv : VSCmm<opcStr, " $vx, "#argStr#", $sy, $sz", opc,
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+ !con(dag_in, (ins simm7:$sy, zero:$sz, RC:$vx))>;
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+ }
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+ multiclass VSCtgm<string opcStr, bits<8>opc, RegisterClass RC> {
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+ let vy = ? in defm v : VSClhm<opcStr, "$vy", opc, RC, (ins V64:$vy)>;
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+ let cs = 1, sw = ? in defm s : VSClhm<opcStr, "$sw", opc, RC, (ins I64:$sw)>;
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+ }
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+ multiclass VSCm<string opcStr, bits<8>opc, RegisterClass RC> {
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+ let vc = 1, cx = 0 in defm "" : VSCtgm<opcStr, opc, RC>;
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+ let vc = 0, cx = 0 in defm NC : VSCtgm<opcStr#".nc", opc, RC>;
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+ let vc = 1, cx = 1 in defm OT : VSCtgm<opcStr#".ot", opc, RC>;
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+ let vc = 0, cx = 1 in defm NCOT : VSCtgm<opcStr#".nc.ot", opc, RC>;
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+ }
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+
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+ // Section 8.9.16 - VSC (Vector Scatter)
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+ defm VSC : VSCm<"vsc", 0xb1, V64>;
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+
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+ // Section 8.9.17 - VSCU (Vector Scatter Upper)
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+ defm VSCU : VSCm<"vscu", 0xb2, V64>;
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+
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+ // Section 8.9.18 - VSCL (Vector Scatter Lower)
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+ defm VSCL : VSCm<"vscl", 0xb3, V64>;
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+
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+ // Section 8.9.19 - PFCHV (Prefetch Vector)
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+ let Uses = [VL] in
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+ multiclass PFCHVbm<string opcStr, string argStr, bits<8>opc, dag dag_in> {
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+ def "" : RVM<opc, (outs), dag_in, !strconcat(opcStr, argStr)>;
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+ let DisableEncoding = "$vl", isCodeGenOnly = 1, VE_VLInUse = 1 in {
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+ def l : RVM<opc, (outs), !con(dag_in, (ins I32:$vl)),
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+ !strconcat(opcStr, argStr)>;
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+ def L : RVM<opc, (outs), !con(dag_in, (ins VLS:$vl)),
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+ !strconcat(opcStr, argStr)>;
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+ }
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+ }
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+ let VE_VLIndex = 2 in
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+ multiclass PFCHVm<string opcStr, bits<8>opc> {
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+ defm rr : PFCHVbm<opcStr, " $sy, $sz", opc, (ins I64:$sy, I64:$sz)>;
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+ let cy = 0 in
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+ defm ir : PFCHVbm<opcStr, " $sy, $sz", opc, (ins simm7:$sy, I64:$sz)>;
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+ let cz = 0 in
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+ defm rz : PFCHVbm<opcStr, " $sy, $sz", opc, (ins I64:$sy, zero:$sz)>;
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+ let cy = 0, cz = 0 in
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+ defm iz : PFCHVbm<opcStr, " $sy, $sz", opc, (ins simm7:$sy, zero:$sz)>;
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+ }
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+ let vc = 1, vx = 0 in defm PFCHV : PFCHVm<"pfchv", 0x80>;
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+ let vc = 0, vx = 0 in defm PFCHVNC : PFCHVm<"pfchv.nc", 0x80>;
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