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[RISCV] Add SMLoc to expanded vector pseudoinstructions in AsmParser. (llvm#84875)
This is needed for llvm-mca to correctly apply vsetvli instruments to these instructions. Fixes llvm#84799.
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3 files changed

+97
-18
lines changed

3 files changed

+97
-18
lines changed

‎llvm/include/llvm/MC/MCInstBuilder.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,12 @@ class MCInstBuilder {
2727
Inst.setOpcode(Opcode);
2828
}
2929

30+
/// Set the location.
31+
MCInstBuilder &setLoc(SMLoc SM) {
32+
Inst.setLoc(SM);
33+
return *this;
34+
}
35+
3036
/// Add a new register operand.
3137
MCInstBuilder &addReg(unsigned Reg) {
3238
Inst.addOperand(MCOperand::createReg(Reg));

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Lines changed: 26 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -3271,11 +3271,13 @@ void RISCVAsmParser::emitVMSGE(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
32713271
.addOperand(Inst.getOperand(0))
32723272
.addOperand(Inst.getOperand(1))
32733273
.addOperand(Inst.getOperand(2))
3274-
.addReg(RISCV::NoRegister));
3274+
.addReg(RISCV::NoRegister)
3275+
.setLoc(IDLoc));
32753276
emitToStreamer(Out, MCInstBuilder(RISCV::VMNAND_MM)
32763277
.addOperand(Inst.getOperand(0))
32773278
.addOperand(Inst.getOperand(0))
3278-
.addOperand(Inst.getOperand(0)));
3279+
.addOperand(Inst.getOperand(0))
3280+
.setLoc(IDLoc));
32793281
} else if (Inst.getNumOperands() == 4) {
32803282
// masked va >= x, vd != v0
32813283
//
@@ -3287,11 +3289,13 @@ void RISCVAsmParser::emitVMSGE(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
32873289
.addOperand(Inst.getOperand(0))
32883290
.addOperand(Inst.getOperand(1))
32893291
.addOperand(Inst.getOperand(2))
3290-
.addOperand(Inst.getOperand(3)));
3292+
.addOperand(Inst.getOperand(3))
3293+
.setLoc(IDLoc));
32913294
emitToStreamer(Out, MCInstBuilder(RISCV::VMXOR_MM)
32923295
.addOperand(Inst.getOperand(0))
32933296
.addOperand(Inst.getOperand(0))
3294-
.addReg(RISCV::V0));
3297+
.addReg(RISCV::V0)
3298+
.setLoc(IDLoc));
32953299
} else if (Inst.getNumOperands() == 5 &&
32963300
Inst.getOperand(0).getReg() == RISCV::V0) {
32973301
// masked va >= x, vd == v0
@@ -3306,11 +3310,13 @@ void RISCVAsmParser::emitVMSGE(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
33063310
.addOperand(Inst.getOperand(1))
33073311
.addOperand(Inst.getOperand(2))
33083312
.addOperand(Inst.getOperand(3))
3309-
.addReg(RISCV::NoRegister));
3313+
.addReg(RISCV::NoRegister)
3314+
.setLoc(IDLoc));
33103315
emitToStreamer(Out, MCInstBuilder(RISCV::VMANDN_MM)
33113316
.addOperand(Inst.getOperand(0))
33123317
.addOperand(Inst.getOperand(0))
3313-
.addOperand(Inst.getOperand(1)));
3318+
.addOperand(Inst.getOperand(1))
3319+
.setLoc(IDLoc));
33143320
} else if (Inst.getNumOperands() == 5) {
33153321
// masked va >= x, any vd
33163322
//
@@ -3323,19 +3329,23 @@ void RISCVAsmParser::emitVMSGE(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
33233329
.addOperand(Inst.getOperand(1))
33243330
.addOperand(Inst.getOperand(2))
33253331
.addOperand(Inst.getOperand(3))
3326-
.addReg(RISCV::NoRegister));
3332+
.addReg(RISCV::NoRegister)
3333+
.setLoc(IDLoc));
33273334
emitToStreamer(Out, MCInstBuilder(RISCV::VMANDN_MM)
33283335
.addOperand(Inst.getOperand(1))
33293336
.addReg(RISCV::V0)
3330-
.addOperand(Inst.getOperand(1)));
3337+
.addOperand(Inst.getOperand(1))
3338+
.setLoc(IDLoc));
33313339
emitToStreamer(Out, MCInstBuilder(RISCV::VMANDN_MM)
33323340
.addOperand(Inst.getOperand(0))
33333341
.addOperand(Inst.getOperand(0))
3334-
.addReg(RISCV::V0));
3342+
.addReg(RISCV::V0)
3343+
.setLoc(IDLoc));
33353344
emitToStreamer(Out, MCInstBuilder(RISCV::VMOR_MM)
33363345
.addOperand(Inst.getOperand(0))
33373346
.addOperand(Inst.getOperand(1))
3338-
.addOperand(Inst.getOperand(0)));
3347+
.addOperand(Inst.getOperand(0))
3348+
.setLoc(IDLoc));
33393349
}
33403350
}
33413351

@@ -3637,7 +3647,8 @@ bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
36373647
.addOperand(Inst.getOperand(0))
36383648
.addOperand(Inst.getOperand(1))
36393649
.addImm(Imm - 1)
3640-
.addOperand(Inst.getOperand(3)));
3650+
.addOperand(Inst.getOperand(3))
3651+
.setLoc(IDLoc));
36413652
return false;
36423653
}
36433654
case RISCV::PseudoVMSGEU_VI:
@@ -3655,7 +3666,8 @@ bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
36553666
.addOperand(Inst.getOperand(0))
36563667
.addOperand(Inst.getOperand(1))
36573668
.addOperand(Inst.getOperand(1))
3658-
.addOperand(Inst.getOperand(3)));
3669+
.addOperand(Inst.getOperand(3))
3670+
.setLoc(IDLoc));
36593671
} else {
36603672
// Other immediate values can subtract one like signed.
36613673
unsigned Opc = Inst.getOpcode() == RISCV::PseudoVMSGEU_VI
@@ -3665,7 +3677,8 @@ bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
36653677
.addOperand(Inst.getOperand(0))
36663678
.addOperand(Inst.getOperand(1))
36673679
.addImm(Imm - 1)
3668-
.addOperand(Inst.getOperand(3)));
3680+
.addOperand(Inst.getOperand(3))
3681+
.setLoc(IDLoc));
36693682
}
36703683

36713684
return false;

‎llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-integer-arithmetic.s

Lines changed: 65 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -399,6 +399,26 @@ vmseq.vv v4, v8, v12
399399
vsetvli zero, zero, e64, m8, tu, mu
400400
vmseq.vx v4, v8, x10
401401

402+
# Pseudo instructions
403+
vsetvli zero, zero, e8, mf8, tu, mu
404+
vmslt.vi v4, v8, 1
405+
vsetvli zero, zero, e8, mf4, tu, mu
406+
vmsltu.vi v4, v8, 1
407+
vsetvli zero, zero, e8, mf2, tu, mu
408+
vmsltu.vi v4, v8, 0
409+
vsetvli zero, zero, e8, m1, tu, mu
410+
vmsgeu.vi v4, v8, 1
411+
vsetvli zero, zero, e8, m2, tu, mu
412+
vmsge.vi v4, v8, 1
413+
vsetvli zero, zero, e8, m4, tu, mu
414+
vmsgeu.vi v4, v8, 0
415+
vsetvli zero, zero, e16, mf4, tu, mu
416+
vmsge.vi v4, v8, 0
417+
vsetvli zero, zero, e16, mf2, tu, mu
418+
vmsge.vx v4, v8, x10
419+
vsetvli zero, zero, e16, m1, tu, mu
420+
vmsgeu.vx v4, v8, x11
421+
402422
# Vector Integer Min/Max Instructions
403423
vsetvli zero, zero, e8, mf8, tu, mu
404424
vminu.vv v4, v8, v12
@@ -754,14 +774,14 @@ vsetvli zero, zero, e64, m8, tu, mu
754774
vmv.v.v v4, v12
755775

756776
# CHECK: Iterations: 1
757-
# CHECK-NEXT: Instructions: 707
758-
# CHECK-NEXT: Total Cycles: 11962
759-
# CHECK-NEXT: Total uOps: 707
777+
# CHECK-NEXT: Instructions: 727
778+
# CHECK-NEXT: Total Cycles: 12018
779+
# CHECK-NEXT: Total uOps: 727
760780

761781
# CHECK: Dispatch Width: 2
762782
# CHECK-NEXT: uOps Per Cycle: 0.06
763783
# CHECK-NEXT: IPC: 0.06
764-
# CHECK-NEXT: Block RThroughput: 11549.0
784+
# CHECK-NEXT: Block RThroughput: 11583.0
765785

766786
# CHECK: Instruction Info:
767787
# CHECK-NEXT: [1]: #uOps
@@ -1144,6 +1164,26 @@ vmv.v.v v4, v12
11441164
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
11451165
# CHECK-NEXT: 1 19 17.00 vmseq.vx v4, v8, a0
11461166
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
1167+
# CHECK-NEXT: 1 4 2.00 vmsle.vi v4, v8, 0
1168+
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
1169+
# CHECK-NEXT: 1 4 2.00 vmsleu.vi v4, v8, 0
1170+
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
1171+
# CHECK-NEXT: 1 4 2.00 vmsne.vv v4, v8, v8
1172+
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
1173+
# CHECK-NEXT: 1 5 3.00 vmsgtu.vi v4, v8, 0
1174+
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
1175+
# CHECK-NEXT: 1 7 5.00 vmsgt.vi v4, v8, 0
1176+
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu
1177+
# CHECK-NEXT: 1 11 9.00 vmseq.vv v4, v8, v8
1178+
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
1179+
# CHECK-NEXT: 1 4 2.00 vmsgt.vi v4, v8, -1
1180+
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
1181+
# CHECK-NEXT: 1 4 2.00 vmslt.vx v4, v8, a0
1182+
# CHECK-NEXT: 1 4 2.00 vmnot.m v4, v4
1183+
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
1184+
# CHECK-NEXT: 1 5 3.00 vmsltu.vx v4, v8, a1
1185+
# CHECK-NEXT: 1 4 2.00 vmnot.m v4, v4
1186+
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
11471187
# CHECK-NEXT: 1 4 2.00 vminu.vv v4, v8, v12
11481188
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
11491189
# CHECK-NEXT: 1 4 2.00 vminu.vx v4, v8, a0
@@ -1492,7 +1532,7 @@ vmv.v.v v4, v12
14921532

14931533
# CHECK: Resource pressure per iteration:
14941534
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
1495-
# CHECK-NEXT: - - 333.00 - 11549.00 374.00 - -
1535+
# CHECK-NEXT: - - 342.00 - 11583.00 385.00 - -
14961536

14971537
# CHECK: Resource pressure by instruction:
14981538
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
@@ -1868,6 +1908,26 @@ vmv.v.v v4, v12
18681908
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
18691909
# CHECK-NEXT: - - - - 17.00 1.00 - - vmseq.vx v4, v8, a0
18701910
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
1911+
# CHECK-NEXT: - - - - 2.00 1.00 - - vmsle.vi v4, v8, 0
1912+
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
1913+
# CHECK-NEXT: - - - - 2.00 1.00 - - vmsleu.vi v4, v8, 0
1914+
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
1915+
# CHECK-NEXT: - - - - 2.00 1.00 - - vmsne.vv v4, v8, v8
1916+
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
1917+
# CHECK-NEXT: - - - - 3.00 1.00 - - vmsgtu.vi v4, v8, 0
1918+
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
1919+
# CHECK-NEXT: - - - - 5.00 1.00 - - vmsgt.vi v4, v8, 0
1920+
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu
1921+
# CHECK-NEXT: - - - - 9.00 1.00 - - vmseq.vv v4, v8, v8
1922+
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
1923+
# CHECK-NEXT: - - - - 2.00 1.00 - - vmsgt.vi v4, v8, -1
1924+
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
1925+
# CHECK-NEXT: - - - - 2.00 1.00 - - vmslt.vx v4, v8, a0
1926+
# CHECK-NEXT: - - - - 2.00 1.00 - - vmnot.m v4, v4
1927+
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
1928+
# CHECK-NEXT: - - - - 3.00 1.00 - - vmsltu.vx v4, v8, a1
1929+
# CHECK-NEXT: - - - - 2.00 1.00 - - vmnot.m v4, v4
1930+
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
18711931
# CHECK-NEXT: - - - - 2.00 1.00 - - vminu.vv v4, v8, v12
18721932
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
18731933
# CHECK-NEXT: - - - - 2.00 1.00 - - vminu.vx v4, v8, a0

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