Skip to content

Commit ad73ce3

Browse files
Ghost-LZWmshockwave
Ghost-LZW
authored and
mshockwave
committed
[Target] use getSubtarget<> instead of static_cast<>(getSubtarget())
Differential Revision: https://reviews.llvm.org/D125391
1 parent bd67468 commit ad73ce3

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

46 files changed

+68
-93
lines changed

‎llvm/include/llvm/CodeGen/SelectionDAG.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -452,6 +452,9 @@ class SelectionDAG {
452452
const DataLayout &getDataLayout() const { return MF->getDataLayout(); }
453453
const TargetMachine &getTarget() const { return TM; }
454454
const TargetSubtargetInfo &getSubtarget() const { return MF->getSubtarget(); }
455+
template <typename STC> const STC &getSubtarget() const {
456+
return MF->getSubtarget<STC>();
457+
}
455458
const TargetLowering &getTargetLoweringInfo() const { return *TLI; }
456459
const TargetLibraryInfo &getLibInfo() const { return *LibInfo; }
457460
const SelectionDAGTargetInfo &getSelectionDAGInfo() const { return *TSI; }

‎llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -132,7 +132,7 @@ class AArch64AsmPrinter : public AsmPrinter {
132132

133133
bool runOnMachineFunction(MachineFunction &MF) override {
134134
AArch64FI = MF.getInfo<AArch64FunctionInfo>();
135-
STI = static_cast<const AArch64Subtarget*>(&MF.getSubtarget());
135+
STI = &MF.getSubtarget<AArch64Subtarget>();
136136

137137
SetupMachineFunction(MF);
138138

‎llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -813,7 +813,7 @@ void FalkorHWPFFix::runOnLoop(MachineLoop &L, MachineFunction &Fn) {
813813
}
814814

815815
bool FalkorHWPFFix::runOnMachineFunction(MachineFunction &Fn) {
816-
auto &ST = static_cast<const AArch64Subtarget &>(Fn.getSubtarget());
816+
auto &ST = Fn.getSubtarget<AArch64Subtarget>();
817817
if (ST.getProcFamily() != AArch64Subtarget::Falkor)
818818
return false;
819819

‎llvm/lib/Target/AArch64/AArch64FastISel.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -283,8 +283,7 @@ class AArch64FastISel final : public FastISel {
283283
explicit AArch64FastISel(FunctionLoweringInfo &FuncInfo,
284284
const TargetLibraryInfo *LibInfo)
285285
: FastISel(FuncInfo, LibInfo, /*SkipTargetIndependentISel=*/true) {
286-
Subtarget =
287-
&static_cast<const AArch64Subtarget &>(FuncInfo.MF->getSubtarget());
286+
Subtarget = &FuncInfo.MF->getSubtarget<AArch64Subtarget>();
288287
Context = &FuncInfo.Fn->getContext();
289288
}
290289

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 10 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -2566,8 +2566,7 @@ static SDValue emitStrictFPComparison(SDValue LHS, SDValue RHS, const SDLoc &dl,
25662566
EVT VT = LHS.getValueType();
25672567
assert(VT != MVT::f128);
25682568

2569-
const bool FullFP16 =
2570-
static_cast<const AArch64Subtarget &>(DAG.getSubtarget()).hasFullFP16();
2569+
const bool FullFP16 = DAG.getSubtarget<AArch64Subtarget>().hasFullFP16();
25712570

25722571
if (VT == MVT::f16 && !FullFP16) {
25732572
LHS = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, {MVT::f32, MVT::Other},
@@ -2585,8 +2584,7 @@ static SDValue emitStrictFPComparison(SDValue LHS, SDValue RHS, const SDLoc &dl,
25852584
static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
25862585
const SDLoc &dl, SelectionDAG &DAG) {
25872586
EVT VT = LHS.getValueType();
2588-
const bool FullFP16 =
2589-
static_cast<const AArch64Subtarget &>(DAG.getSubtarget()).hasFullFP16();
2587+
const bool FullFP16 = DAG.getSubtarget<AArch64Subtarget>().hasFullFP16();
25902588

25912589
if (VT.isFloatingPoint()) {
25922590
assert(VT != MVT::f128);
@@ -2694,8 +2692,7 @@ static SDValue emitConditionalComparison(SDValue LHS, SDValue RHS,
26942692
AArch64CC::CondCode OutCC,
26952693
const SDLoc &DL, SelectionDAG &DAG) {
26962694
unsigned Opcode = 0;
2697-
const bool FullFP16 =
2698-
static_cast<const AArch64Subtarget &>(DAG.getSubtarget()).hasFullFP16();
2695+
const bool FullFP16 = DAG.getSubtarget<AArch64Subtarget>().hasFullFP16();
26992696

27002697
if (LHS.getValueType().isFloatingPoint()) {
27012698
assert(LHS.getValueType() != MVT::f128);
@@ -11865,8 +11862,7 @@ SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
1186511862
return DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
1186611863
}
1186711864

11868-
const bool FullFP16 =
11869-
static_cast<const AArch64Subtarget &>(DAG.getSubtarget()).hasFullFP16();
11865+
const bool FullFP16 = DAG.getSubtarget<AArch64Subtarget>().hasFullFP16();
1187011866

1187111867
// Make v4f16 (only) fcmp operations utilise vector instructions
1187211868
// v8f16 support will be a litle more complicated
@@ -12000,7 +11996,7 @@ SDValue AArch64TargetLowering::LowerVECREDUCE(SDValue Op,
1200011996

1200111997
SDValue AArch64TargetLowering::LowerATOMIC_LOAD_SUB(SDValue Op,
1200211998
SelectionDAG &DAG) const {
12003-
auto &Subtarget = static_cast<const AArch64Subtarget &>(DAG.getSubtarget());
11999+
auto &Subtarget = DAG.getSubtarget<AArch64Subtarget>();
1200412000
if (!Subtarget.hasLSE() && !Subtarget.outlineAtomics())
1200512001
return SDValue();
1200612002

@@ -12017,7 +12013,7 @@ SDValue AArch64TargetLowering::LowerATOMIC_LOAD_SUB(SDValue Op,
1201712013

1201812014
SDValue AArch64TargetLowering::LowerATOMIC_LOAD_AND(SDValue Op,
1201912015
SelectionDAG &DAG) const {
12020-
auto &Subtarget = static_cast<const AArch64Subtarget &>(DAG.getSubtarget());
12016+
auto &Subtarget = DAG.getSubtarget<AArch64Subtarget>();
1202112017
if (!Subtarget.hasLSE() && !Subtarget.outlineAtomics())
1202212018
return SDValue();
1202312019

@@ -14797,8 +14793,7 @@ performExtractVectorEltCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
1479714793
ConstantSDNode *ConstantN1 = dyn_cast<ConstantSDNode>(N1);
1479814794

1479914795
EVT VT = N->getValueType(0);
14800-
const bool FullFP16 =
14801-
static_cast<const AArch64Subtarget &>(DAG.getSubtarget()).hasFullFP16();
14796+
const bool FullFP16 = DAG.getSubtarget<AArch64Subtarget>().hasFullFP16();
1480214797
bool IsStrict = N0->isStrictFPOpcode();
1480314798

1480414799
// Rewrite for pairwise fadd pattern
@@ -16009,8 +16004,7 @@ static bool isAllActivePredicate(SelectionDAG &DAG, SDValue N) {
1600916004
// If we're compiling for a specific vector-length, we can check if the
1601016005
// pattern's VL equals that of the scalable vector at runtime.
1601116006
if (N.getOpcode() == AArch64ISD::PTRUE) {
16012-
const auto &Subtarget =
16013-
static_cast<const AArch64Subtarget &>(DAG.getSubtarget());
16007+
const auto &Subtarget = DAG.getSubtarget<AArch64Subtarget>();
1601416008
unsigned MinSVESize = Subtarget.getMinSVEVectorSizeInBits();
1601516009
unsigned MaxSVESize = Subtarget.getMaxSVEVectorSizeInBits();
1601616010
if (MaxSVESize && MinSVESize == MaxSVESize) {
@@ -17231,8 +17225,7 @@ static bool findMoreOptimalIndexType(const MaskedGatherScatterSDNode *N,
1723117225
Stride > std::numeric_limits<int32_t>::max())
1723217226
return Changed;
1723317227

17234-
const auto &Subtarget =
17235-
static_cast<const AArch64Subtarget &>(DAG.getSubtarget());
17228+
const auto &Subtarget = DAG.getSubtarget<AArch64Subtarget>();
1723617229
unsigned MaxVScale =
1723717230
Subtarget.getMaxSVEVectorSizeInBits() / AArch64::SVEBitsPerBlock;
1723817231
int64_t LastElementOffset =
@@ -20219,8 +20212,7 @@ static SDValue getPredicateForFixedLengthVector(SelectionDAG &DAG, SDLoc &DL,
2021920212
// For vectors that are exactly getMaxSVEVectorSizeInBits big, we can use
2022020213
// AArch64SVEPredPattern::all, which can enable the use of unpredicated
2022120214
// variants of instructions when available.
20222-
const auto &Subtarget =
20223-
static_cast<const AArch64Subtarget &>(DAG.getSubtarget());
20215+
const auto &Subtarget = DAG.getSubtarget<AArch64Subtarget>();
2022420216
unsigned MinSVESize = Subtarget.getMinSVEVectorSizeInBits();
2022520217
unsigned MaxSVESize = Subtarget.getMaxSVEVectorSizeInBits();
2022620218
if (MaxSVESize && MinSVESize == MaxSVESize &&

‎llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2308,7 +2308,7 @@ bool AArch64LoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
23082308
if (skipFunction(Fn.getFunction()))
23092309
return false;
23102310

2311-
Subtarget = &static_cast<const AArch64Subtarget &>(Fn.getSubtarget());
2311+
Subtarget = &Fn.getSubtarget<AArch64Subtarget>();
23122312
TII = static_cast<const AArch64InstrInfo *>(Subtarget->getInstrInfo());
23132313
TRI = Subtarget->getRegisterInfo();
23142314
AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();

‎llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2335,8 +2335,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
23352335
MachineFunction &MF = *MBB.getParent();
23362336
MachineRegisterInfo &MRI = MF.getRegInfo();
23372337

2338-
const AArch64Subtarget *Subtarget =
2339-
&static_cast<const AArch64Subtarget &>(MF.getSubtarget());
2338+
const AArch64Subtarget *Subtarget = &MF.getSubtarget<AArch64Subtarget>();
23402339
if (Subtarget->requiresStrictAlign()) {
23412340
// We don't support this feature yet.
23422341
LLVM_DEBUG(dbgs() << "AArch64 GISel does not support strict-align yet\n");

‎llvm/lib/Target/ARM/ARMBlockPlacement.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -213,7 +213,7 @@ bool ARMBlockPlacement::processPostOrderLoops(MachineLoop *ML) {
213213
bool ARMBlockPlacement::runOnMachineFunction(MachineFunction &MF) {
214214
if (skipFunction(MF.getFunction()))
215215
return false;
216-
const ARMSubtarget &ST = static_cast<const ARMSubtarget &>(MF.getSubtarget());
216+
const ARMSubtarget &ST = MF.getSubtarget<ARMSubtarget>();
217217
if (!ST.hasLOB())
218218
return false;
219219
LLVM_DEBUG(dbgs() << DEBUG_PREFIX << "Running on " << MF.getName() << "\n");

‎llvm/lib/Target/ARM/ARMConstantIslandPass.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -396,7 +396,7 @@ bool ARMConstantIslands::runOnMachineFunction(MachineFunction &mf) {
396396
<< MCP->getConstants().size() << " CP entries, aligned to "
397397
<< MCP->getConstantPoolAlign().value() << " bytes *****\n");
398398

399-
STI = &static_cast<const ARMSubtarget &>(MF->getSubtarget());
399+
STI = &MF->getSubtarget<ARMSubtarget>();
400400
TII = STI->getInstrInfo();
401401
isPositionIndependentOrROPI =
402402
STI->getTargetLowering()->isPositionIndependent() || STI->isROPI();

‎llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3132,7 +3132,7 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
31323132
}
31333133

31343134
bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
3135-
STI = &static_cast<const ARMSubtarget &>(MF.getSubtarget());
3135+
STI = &MF.getSubtarget<ARMSubtarget>();
31363136
TII = STI->getInstrInfo();
31373137
TRI = STI->getRegisterInfo();
31383138
AFI = MF.getInfo<ARMFunctionInfo>();

‎llvm/lib/Target/ARM/ARMFastISel.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -122,8 +122,7 @@ class ARMFastISel final : public FastISel {
122122
explicit ARMFastISel(FunctionLoweringInfo &funcInfo,
123123
const TargetLibraryInfo *libInfo)
124124
: FastISel(funcInfo, libInfo),
125-
Subtarget(
126-
&static_cast<const ARMSubtarget &>(funcInfo.MF->getSubtarget())),
125+
Subtarget(&funcInfo.MF->getSubtarget<ARMSubtarget>()),
127126
M(const_cast<Module &>(*funcInfo.Fn->getParent())),
128127
TM(funcInfo.MF->getTarget()), TII(*Subtarget->getInstrInfo()),
129128
TLI(*Subtarget->getTargetLowering()) {
@@ -156,7 +155,7 @@ class ARMFastISel final : public FastISel {
156155
const LoadInst *LI) override;
157156
bool fastLowerArguments() override;
158157

159-
#include "ARMGenFastISel.inc"
158+
#include "ARMGenFastISel.inc"
160159

161160
// Instruction selection routines.
162161

‎llvm/lib/Target/ARM/ARMFrameLowering.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -392,8 +392,7 @@ static void emitAligningInstructions(MachineFunction &MF, ARMFunctionInfo *AFI,
392392
const DebugLoc &DL, const unsigned Reg,
393393
const Align Alignment,
394394
const bool MustBeSingleInstruction) {
395-
const ARMSubtarget &AST =
396-
static_cast<const ARMSubtarget &>(MF.getSubtarget());
395+
const ARMSubtarget &AST = MF.getSubtarget<ARMSubtarget>();
397396
const bool CanUseBFC = AST.hasV6T2Ops() || AST.hasV7Ops();
398397
const unsigned AlignMask = Alignment.value() - 1U;
399398
const unsigned NrBitsToZero = Log2(Alignment);
@@ -1768,7 +1767,7 @@ checkNumAlignedDPRCS2Regs(MachineFunction &MF, BitVector &SavedRegs) {
17681767
return;
17691768

17701769
// We are planning to use NEON instructions vst1 / vld1.
1771-
if (!static_cast<const ARMSubtarget &>(MF.getSubtarget()).hasNEON())
1770+
if (!MF.getSubtarget<ARMSubtarget>().hasNEON())
17721771
return;
17731772

17741773
// Don't bother if the default stack alignment is sufficiently high.

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -5807,8 +5807,7 @@ static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
58075807
return DAG.UnrollVectorOp(Op.getNode());
58085808
}
58095809

5810-
const bool HasFullFP16 =
5811-
static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16();
5810+
const bool HasFullFP16 = DAG.getSubtarget<ARMSubtarget>().hasFullFP16();
58125811

58135812
EVT NewTy;
58145813
const EVT OpTy = Op.getOperand(0).getValueType();
@@ -5918,8 +5917,7 @@ static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
59185917
Op.getOperand(0).getValueType() == MVT::v8i16) &&
59195918
"Invalid type for custom lowering!");
59205919

5921-
const bool HasFullFP16 =
5922-
static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16();
5920+
const bool HasFullFP16 = DAG.getSubtarget<ARMSubtarget>().hasFullFP16();
59235921

59245922
EVT DestVecType;
59255923
if (VT == MVT::v4f32)
@@ -9882,7 +9880,7 @@ ARMTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
98829880
if (N->getOpcode() != ISD::SDIV)
98839881
return SDValue();
98849882

9885-
const auto &ST = static_cast<const ARMSubtarget&>(DAG.getSubtarget());
9883+
const auto &ST = DAG.getSubtarget<ARMSubtarget>();
98869884
const bool MinSize = ST.hasMinSize();
98879885
const bool HasDivide = ST.isThumb() ? ST.hasDivideInThumbMode()
98889886
: ST.hasDivideInARMMode();

‎llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2110,7 +2110,7 @@ bool ARMLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
21102110
return false;
21112111

21122112
MF = &Fn;
2113-
STI = &static_cast<const ARMSubtarget &>(Fn.getSubtarget());
2113+
STI = &Fn.getSubtarget<ARMSubtarget>();
21142114
TL = STI->getTargetLowering();
21152115
AFI = Fn.getInfo<ARMFunctionInfo>();
21162116
TII = STI->getInstrInfo();
@@ -2201,7 +2201,7 @@ bool ARMPreAllocLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
22012201
return false;
22022202

22032203
TD = &Fn.getDataLayout();
2204-
STI = &static_cast<const ARMSubtarget &>(Fn.getSubtarget());
2204+
STI = &Fn.getSubtarget<ARMSubtarget>();
22052205
TII = STI->getInstrInfo();
22062206
TRI = STI->getRegisterInfo();
22072207
MRI = &Fn.getRegInfo();

‎llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1299,7 +1299,7 @@ bool LowOverheadLoop::ValidateMVEInst(MachineInstr *MI) {
12991299
}
13001300

13011301
bool ARMLowOverheadLoops::runOnMachineFunction(MachineFunction &mf) {
1302-
const ARMSubtarget &ST = static_cast<const ARMSubtarget&>(mf.getSubtarget());
1302+
const ARMSubtarget &ST = mf.getSubtarget<ARMSubtarget>();
13031303
if (!ST.hasLOB())
13041304
return false;
13051305

‎llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1052,8 +1052,7 @@ bool MVETPAndVPTOptimisations::HintDoLoopStartReg(MachineBasicBlock &MBB) {
10521052
}
10531053

10541054
bool MVETPAndVPTOptimisations::runOnMachineFunction(MachineFunction &Fn) {
1055-
const ARMSubtarget &STI =
1056-
static_cast<const ARMSubtarget &>(Fn.getSubtarget());
1055+
const ARMSubtarget &STI = Fn.getSubtarget<ARMSubtarget>();
10571056

10581057
if (!STI.isThumb2() || !STI.hasLOB())
10591058
return false;

‎llvm/lib/Target/ARM/MVEVPTBlockPass.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -312,8 +312,7 @@ bool MVEVPTBlock::InsertVPTBlocks(MachineBasicBlock &Block) {
312312
}
313313

314314
bool MVEVPTBlock::runOnMachineFunction(MachineFunction &Fn) {
315-
const ARMSubtarget &STI =
316-
static_cast<const ARMSubtarget &>(Fn.getSubtarget());
315+
const ARMSubtarget &STI = Fn.getSubtarget<ARMSubtarget>();
317316

318317
if (!STI.isThumb2() || !STI.hasMVEIntegerOps())
319318
return false;

‎llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -284,8 +284,7 @@ bool Thumb2ITBlock::InsertITInstructions(MachineBasicBlock &MBB) {
284284
}
285285

286286
bool Thumb2ITBlock::runOnMachineFunction(MachineFunction &Fn) {
287-
const ARMSubtarget &STI =
288-
static_cast<const ARMSubtarget &>(Fn.getSubtarget());
287+
const ARMSubtarget &STI = Fn.getSubtarget<ARMSubtarget>();
289288
if (!STI.isThumb2())
290289
return false;
291290
AFI = Fn.getInfo<ARMFunctionInfo>();

‎llvm/lib/Target/ARM/Thumb2SizeReduction.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1130,7 +1130,7 @@ bool Thumb2SizeReduce::runOnMachineFunction(MachineFunction &MF) {
11301130
if (PredicateFtor && !PredicateFtor(MF.getFunction()))
11311131
return false;
11321132

1133-
STI = &static_cast<const ARMSubtarget &>(MF.getSubtarget());
1133+
STI = &MF.getSubtarget<ARMSubtarget>();
11341134
if (STI->isThumb1Only() || STI->prefers32BitThumb())
11351135
return false;
11361136

‎llvm/lib/Target/CSKY/CSKYConstantIslandPass.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -287,7 +287,7 @@ LLVM_DUMP_METHOD void CSKYConstantIslands::dumpBBs() {
287287
bool CSKYConstantIslands::runOnMachineFunction(MachineFunction &Mf) {
288288
MF = &Mf;
289289
MCP = Mf.getConstantPool();
290-
STI = &static_cast<const CSKYSubtarget &>(Mf.getSubtarget());
290+
STI = &Mf.getSubtarget<CSKYSubtarget>();
291291

292292
LLVM_DEBUG(dbgs() << "***** CSKYConstantIslands: "
293293
<< MCP->getConstants().size() << " CP entries, aligned to "

‎llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -801,7 +801,7 @@ static const HexagonTargetLowering &getHexagonLowering(SelectionDAG &G) {
801801
return static_cast<const HexagonTargetLowering&>(G.getTargetLoweringInfo());
802802
}
803803
static const HexagonSubtarget &getHexagonSubtarget(SelectionDAG &G) {
804-
return static_cast<const HexagonSubtarget&>(G.getSubtarget());
804+
return G.getSubtarget<HexagonSubtarget>();
805805
}
806806

807807
namespace llvm {

‎llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1396,10 +1396,9 @@ HexagonTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
13961396
Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, Hexagon::R0, Chain, InFlag);
13971397
InFlag = Chain.getValue(1);
13981398

1399-
unsigned Flags =
1400-
static_cast<const HexagonSubtarget &>(DAG.getSubtarget()).useLongCalls()
1401-
? HexagonII::MO_GDPLT | HexagonII::HMOTF_ConstExtended
1402-
: HexagonII::MO_GDPLT;
1399+
unsigned Flags = DAG.getSubtarget<HexagonSubtarget>().useLongCalls()
1400+
? HexagonII::MO_GDPLT | HexagonII::HMOTF_ConstExtended
1401+
: HexagonII::MO_GDPLT;
14031402

14041403
return GetDynamicTLSAddr(DAG, Chain, GA, InFlag, PtrVT,
14051404
Hexagon::R0, Flags);

‎llvm/lib/Target/Hexagon/HexagonPatternsHVX.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ def SDTHexagonVINSERTW0: SDTypeProfile<1, 2,
3737
def HexagonVINSERTW0: SDNode<"HexagonISD::VINSERTW0", SDTHexagonVINSERTW0>;
3838

3939
def HwLen2: SDNodeXForm<imm, [{
40-
const auto &ST = static_cast<const HexagonSubtarget&>(CurDAG->getSubtarget());
40+
const auto &ST = CurDAG->getSubtarget<HexagonSubtarget>();
4141
return CurDAG->getTargetConstant(ST.getVectorLength()/2, SDLoc(N), MVT::i32);
4242
}]>;
4343

‎llvm/lib/Target/M68k/M68kCollapseMOVEMPass.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -231,7 +231,7 @@ class M68kCollapseMOVEM : public MachineFunctionPass {
231231
}
232232

233233
bool runOnMachineFunction(MachineFunction &MF) override {
234-
STI = &static_cast<const M68kSubtarget &>(MF.getSubtarget());
234+
STI = &MF.getSubtarget<M68kSubtarget>();
235235
TII = STI->getInstrInfo();
236236
TRI = STI->getRegisterInfo();
237237
MFI = MF.getInfo<M68kMachineFunctionInfo>();

‎llvm/lib/Target/M68k/M68kExpandPseudo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -302,7 +302,7 @@ bool M68kExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
302302
}
303303

304304
bool M68kExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
305-
STI = &static_cast<const M68kSubtarget &>(MF.getSubtarget());
305+
STI = &MF.getSubtarget<M68kSubtarget>();
306306
TII = STI->getInstrInfo();
307307
TRI = STI->getRegisterInfo();
308308
MFI = MF.getInfo<M68kMachineFunctionInfo>();

‎llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -312,7 +312,7 @@ class M68kDAGToDAGISel : public SelectionDAGISel {
312312
} // namespace
313313

314314
bool M68kDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
315-
Subtarget = &static_cast<const M68kSubtarget &>(MF.getSubtarget());
315+
Subtarget = &MF.getSubtarget<M68kSubtarget>();
316316
return SelectionDAGISel::runOnMachineFunction(MF);
317317
}
318318

‎llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -774,7 +774,7 @@ bool MicroMipsSizeReduce::ReplaceInstruction(MachineInstr *MI,
774774

775775
bool MicroMipsSizeReduce::runOnMachineFunction(MachineFunction &MF) {
776776

777-
Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
777+
Subtarget = &MF.getSubtarget<MipsSubtarget>();
778778

779779
// TODO: Add support for the subtarget microMIPS32R6.
780780
if (!Subtarget->inMicroMipsMode() || !Subtarget->hasMips32r2() ||

0 commit comments

Comments
 (0)