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1 parent 3bd8f4e commit b1b436cCopy full SHA for b1b436c
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -534,7 +534,7 @@ static InstructionCost getHistogramCost(const IntrinsicCostAttributes &ICA) {
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// HistCnt only supports 32b and 64b element types
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unsigned LegalEltSize = EltSize <= 32 ? 32 : 64;
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- if (EC == 2 || (!LegalEltSize == 32 && EC == 4))
+ if (EC == 2 || (LegalEltSize == 32 && EC == 4))
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return InstructionCost(BaseHistCntCost);
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unsigned NaturalVectorWidth = AArch64::SVEBitsPerBlock / LegalEltSize;
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