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[globalisel] Support trivial COPY in GISelKnownBits
Summary: Allow GISelKnownBits to look through the trivial case of TargetOpcode::COPY Reviewers: aditya_nandakumar Subscribers: rovka, hiraditya, volkan, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67131 llvm-svn: 370955
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llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp

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@@ -112,6 +112,19 @@ void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known,
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default:
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TL.computeKnownBitsForTargetInstr(R, Known, DemandedElts, MRI, Depth);
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break;
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case TargetOpcode::COPY: {
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MachineOperand Dst = MI.getOperand(0);
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MachineOperand Src = MI.getOperand(1);
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// Look through trivial copies.
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// We can't use NoSubRegister by name as it's defined by each target but
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// it's always defined to be 0 by tablegen.
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if (Dst.getSubReg() == 0 /*NoSubRegister*/ && Src.getReg().isVirtual() &&
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Src.getSubReg() == 0 /*NoSubRegister*/) {
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// Don't increment Depth for this one since we didn't do any work.
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computeKnownBitsImpl(Src.getReg(), Known, DemandedElts, Depth);
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}
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break;
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}
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case TargetOpcode::G_CONSTANT: {
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auto CstVal = getConstantVRegVal(R, MRI);
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Known.One = *CstVal;

llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp

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@@ -19,11 +19,17 @@ TEST_F(GISelMITest, TestKnownBitsCst) {
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unsigned CopyReg = Copies[Copies.size() - 1];
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MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
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unsigned SrcReg = FinalCopy->getOperand(1).getReg();
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unsigned DstReg = FinalCopy->getOperand(1).getReg();
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GISelKnownBits Info(*MF);
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KnownBits Res = Info.getKnownBits(SrcReg);
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EXPECT_EQ((uint64_t)1, Res.One.getZExtValue());
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EXPECT_EQ((uint64_t)0xfe, Res.Zero.getZExtValue());
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KnownBits Res2 = Info.getKnownBits(DstReg);
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EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
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EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
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}
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TEST_F(GISelMITest, TestKnownBitsPtrToIntViceVersa) {
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StringRef MIRString = " %3:_(s16) = G_CONSTANT i16 256\n"
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" %4:_(p0) = G_INTTOPTR %3\n"

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