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[RISCV] Enable scalable loop vectorization for zvfhmin/zvfbfmin (llvm#115272)
This PR enables scalable loop vectorization for f16 with zvfhmin and bf16 with zvfbfmin. Enabling this was dependent on filling out the gaps for scalable zvfhmin/zvfbfmin codegen, but everything that the loop vectorizer might emit should now be handled. It does this by marking f16 and bf16 as legal in `isLegalElementTypeForRVV`. There are a few users of `isLegalElementTypeForRVV` that have already been enabled in other PRs: - `isLegalStridedLoadStore` llvm#115264 - `isLegalInterleavedAccessType` llvm#115257 - `isLegalMaskedLoadStore` llvm#115145 - `isLegalMaskedGatherScatter` llvm#114945 The remaining user is `isLegalToVectorizeReduction`. We can't promote f16/bf16 reductions to f32 so we need to disable them for scalable vectors. The cost model actually marks these as invalid, but for out-of-tree reductions `ComputeReductionResult` doesn't get costed and it will end up emitting a reduction intrinsic regardless, so we still need to mark them as illegal. We might be able to remove this restriction later for fmax and fmin reductions.
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5 files changed

+502
-24
lines changed

5 files changed

+502
-24
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 5 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -2516,7 +2516,9 @@ bool RISCVTargetLowering::isLegalElementTypeForRVV(EVT ScalarTy) const {
25162516
case MVT::i64:
25172517
return Subtarget.hasVInstructionsI64();
25182518
case MVT::f16:
2519-
return Subtarget.hasVInstructionsF16();
2519+
return Subtarget.hasVInstructionsF16Minimal();
2520+
case MVT::bf16:
2521+
return Subtarget.hasVInstructionsBF16Minimal();
25202522
case MVT::f32:
25212523
return Subtarget.hasVInstructionsF32();
25222524
case MVT::f64:
@@ -21519,12 +21521,7 @@ bool RISCVTargetLowering::isLegalInterleavedAccessType(
2151921521
if (!isTypeLegal(VT))
2152021522
return false;
2152121523

21522-
// TODO: Move bf16/f16 support into isLegalElementTypeForRVV
21523-
if (!(isLegalElementTypeForRVV(VT.getScalarType()) ||
21524-
(VT.getScalarType() == MVT::bf16 &&
21525-
Subtarget.hasVInstructionsBF16Minimal()) ||
21526-
(VT.getScalarType() == MVT::f16 &&
21527-
Subtarget.hasVInstructionsF16Minimal())) ||
21524+
if (!isLegalElementTypeForRVV(VT.getScalarType()) ||
2152821525
!allowsMemoryAccessForAlignment(VTy->getContext(), DL, VT, AddrSpace,
2152921526
Alignment))
2153021527
return false;
@@ -21564,10 +21561,7 @@ bool RISCVTargetLowering::isLegalStridedLoadStore(EVT DataType,
2156421561
return false;
2156521562

2156621563
EVT ScalarType = DataType.getScalarType();
21567-
// TODO: Move bf16/f16 support into isLegalElementTypeForRVV
21568-
if (!(isLegalElementTypeForRVV(ScalarType) ||
21569-
(ScalarType == MVT::bf16 && Subtarget.hasVInstructionsBF16Minimal()) ||
21570-
(ScalarType == MVT::f16 && Subtarget.hasVInstructionsF16Minimal())))
21564+
if (!isLegalElementTypeForRVV(ScalarType))
2157121565
return false;
2157221566

2157321567
if (!Subtarget.enableUnalignedVectorMem() &&

‎llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h

Lines changed: 8 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -239,12 +239,7 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
239239
if (!ST->enableUnalignedVectorMem() && Alignment < ElemType.getStoreSize())
240240
return false;
241241

242-
// TODO: Move bf16/f16 support into isLegalElementTypeForRVV
243-
return TLI->isLegalElementTypeForRVV(ElemType) ||
244-
(DataTypeVT.getVectorElementType() == MVT::bf16 &&
245-
ST->hasVInstructionsBF16Minimal()) ||
246-
(DataTypeVT.getVectorElementType() == MVT::f16 &&
247-
ST->hasVInstructionsF16Minimal());
242+
return TLI->isLegalElementTypeForRVV(ElemType);
248243
}
249244

250245
bool isLegalMaskedLoad(Type *DataType, Align Alignment) {
@@ -274,12 +269,7 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
274269
if (!ST->enableUnalignedVectorMem() && Alignment < ElemType.getStoreSize())
275270
return false;
276271

277-
// TODO: Move bf16/f16 support into isLegalElementTypeForRVV
278-
return TLI->isLegalElementTypeForRVV(ElemType) ||
279-
(DataTypeVT.getVectorElementType() == MVT::bf16 &&
280-
ST->hasVInstructionsBF16Minimal()) ||
281-
(DataTypeVT.getVectorElementType() == MVT::f16 &&
282-
ST->hasVInstructionsF16Minimal());
272+
return TLI->isLegalElementTypeForRVV(ElemType);
283273
}
284274

285275
bool isLegalMaskedGather(Type *DataType, Align Alignment) {
@@ -341,6 +331,12 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
341331
if (!TLI->isLegalElementTypeForRVV(TLI->getValueType(DL, Ty)))
342332
return false;
343333

334+
// We can't promote f16/bf16 fadd reductions and scalable vectors can't be
335+
// expanded.
336+
// TODO: Promote f16/bf16 fmin/fmax reductions
337+
if (Ty->isBFloatTy() || (Ty->isHalfTy() && !ST->hasVInstructionsF16()))
338+
return false;
339+
344340
switch (RdxDesc.getRecurrenceKind()) {
345341
case RecurKind::Add:
346342
case RecurKind::FAdd:

‎llvm/test/Transforms/LoopVectorize/RISCV/bf16.ll

Lines changed: 233 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,233 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2+
; RUN: opt < %s -passes=loop-vectorize -mtriple riscv64 -mattr=+v -S | FileCheck %s -check-prefix=NO-ZVFBFMIN
3+
; RUN: opt < %s -passes=loop-vectorize -mtriple riscv64 -mattr=+v,+zvfbfmin -S | FileCheck %s -check-prefix=ZVFBFMIN
4+
5+
define void @fadd(ptr noalias %a, ptr noalias %b, i64 %n) {
6+
; NO-ZVFBFMIN-LABEL: define void @fadd(
7+
; NO-ZVFBFMIN-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
8+
; NO-ZVFBFMIN-NEXT: [[ENTRY:.*]]:
9+
; NO-ZVFBFMIN-NEXT: br label %[[LOOP:.*]]
10+
; NO-ZVFBFMIN: [[LOOP]]:
11+
; NO-ZVFBFMIN-NEXT: [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[I_NEXT:%.*]], %[[LOOP]] ]
12+
; NO-ZVFBFMIN-NEXT: [[A_GEP:%.*]] = getelementptr bfloat, ptr [[A]], i64 [[I]]
13+
; NO-ZVFBFMIN-NEXT: [[B_GEP:%.*]] = getelementptr bfloat, ptr [[B]], i64 [[I]]
14+
; NO-ZVFBFMIN-NEXT: [[X:%.*]] = load bfloat, ptr [[A_GEP]], align 2
15+
; NO-ZVFBFMIN-NEXT: [[Y:%.*]] = load bfloat, ptr [[B_GEP]], align 2
16+
; NO-ZVFBFMIN-NEXT: [[Z:%.*]] = fadd bfloat [[X]], [[Y]]
17+
; NO-ZVFBFMIN-NEXT: store bfloat [[Z]], ptr [[A_GEP]], align 2
18+
; NO-ZVFBFMIN-NEXT: [[I_NEXT]] = add i64 [[I]], 1
19+
; NO-ZVFBFMIN-NEXT: [[DONE:%.*]] = icmp eq i64 [[I_NEXT]], [[N]]
20+
; NO-ZVFBFMIN-NEXT: br i1 [[DONE]], label %[[EXIT:.*]], label %[[LOOP]]
21+
; NO-ZVFBFMIN: [[EXIT]]:
22+
; NO-ZVFBFMIN-NEXT: ret void
23+
;
24+
; ZVFBFMIN-LABEL: define void @fadd(
25+
; ZVFBFMIN-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
26+
; ZVFBFMIN-NEXT: [[ENTRY:.*]]:
27+
; ZVFBFMIN-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()
28+
; ZVFBFMIN-NEXT: [[TMP8:%.*]] = mul i64 [[TMP7]], 8
29+
; ZVFBFMIN-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], [[TMP8]]
30+
; ZVFBFMIN-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
31+
; ZVFBFMIN: [[VECTOR_PH]]:
32+
; ZVFBFMIN-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
33+
; ZVFBFMIN-NEXT: [[TMP10:%.*]] = mul i64 [[TMP9]], 8
34+
; ZVFBFMIN-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP10]]
35+
; ZVFBFMIN-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
36+
; ZVFBFMIN-NEXT: [[TMP12:%.*]] = call i64 @llvm.vscale.i64()
37+
; ZVFBFMIN-NEXT: [[TMP5:%.*]] = mul i64 [[TMP12]], 8
38+
; ZVFBFMIN-NEXT: br label %[[VECTOR_BODY:.*]]
39+
; ZVFBFMIN: [[VECTOR_BODY]]:
40+
; ZVFBFMIN-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
41+
; ZVFBFMIN-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0
42+
; ZVFBFMIN-NEXT: [[TMP1:%.*]] = getelementptr bfloat, ptr [[A]], i64 [[TMP0]]
43+
; ZVFBFMIN-NEXT: [[TMP2:%.*]] = getelementptr bfloat, ptr [[B]], i64 [[TMP0]]
44+
; ZVFBFMIN-NEXT: [[TMP3:%.*]] = getelementptr bfloat, ptr [[TMP1]], i32 0
45+
; ZVFBFMIN-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x bfloat>, ptr [[TMP3]], align 2
46+
; ZVFBFMIN-NEXT: [[TMP4:%.*]] = getelementptr bfloat, ptr [[TMP2]], i32 0
47+
; ZVFBFMIN-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x bfloat>, ptr [[TMP4]], align 2
48+
; ZVFBFMIN-NEXT: [[TMP11:%.*]] = fadd <vscale x 8 x bfloat> [[WIDE_LOAD]], [[WIDE_LOAD1]]
49+
; ZVFBFMIN-NEXT: store <vscale x 8 x bfloat> [[TMP11]], ptr [[TMP3]], align 2
50+
; ZVFBFMIN-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP5]]
51+
; ZVFBFMIN-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
52+
; ZVFBFMIN-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
53+
; ZVFBFMIN: [[MIDDLE_BLOCK]]:
54+
; ZVFBFMIN-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
55+
; ZVFBFMIN-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
56+
; ZVFBFMIN: [[SCALAR_PH]]:
57+
; ZVFBFMIN-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
58+
; ZVFBFMIN-NEXT: br label %[[LOOP:.*]]
59+
; ZVFBFMIN: [[LOOP]]:
60+
; ZVFBFMIN-NEXT: [[I:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[I_NEXT:%.*]], %[[LOOP]] ]
61+
; ZVFBFMIN-NEXT: [[A_GEP:%.*]] = getelementptr bfloat, ptr [[A]], i64 [[I]]
62+
; ZVFBFMIN-NEXT: [[B_GEP:%.*]] = getelementptr bfloat, ptr [[B]], i64 [[I]]
63+
; ZVFBFMIN-NEXT: [[X:%.*]] = load bfloat, ptr [[A_GEP]], align 2
64+
; ZVFBFMIN-NEXT: [[Y:%.*]] = load bfloat, ptr [[B_GEP]], align 2
65+
; ZVFBFMIN-NEXT: [[Z:%.*]] = fadd bfloat [[X]], [[Y]]
66+
; ZVFBFMIN-NEXT: store bfloat [[Z]], ptr [[A_GEP]], align 2
67+
; ZVFBFMIN-NEXT: [[I_NEXT]] = add i64 [[I]], 1
68+
; ZVFBFMIN-NEXT: [[DONE:%.*]] = icmp eq i64 [[I_NEXT]], [[N]]
69+
; ZVFBFMIN-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
70+
; ZVFBFMIN: [[EXIT]]:
71+
; ZVFBFMIN-NEXT: ret void
72+
;
73+
entry:
74+
br label %loop
75+
loop:
76+
%i = phi i64 [0, %entry], [%i.next, %loop]
77+
%a.gep = getelementptr bfloat, ptr %a, i64 %i
78+
%b.gep = getelementptr bfloat, ptr %b, i64 %i
79+
%x = load bfloat, ptr %a.gep
80+
%y = load bfloat, ptr %b.gep
81+
%z = fadd bfloat %x, %y
82+
store bfloat %z, ptr %a.gep
83+
%i.next = add i64 %i, 1
84+
%done = icmp eq i64 %i.next, %n
85+
br i1 %done, label %exit, label %loop
86+
exit:
87+
ret void
88+
}
89+
90+
define void @vfwmaccbf16.vv(ptr noalias %a, ptr noalias %b, ptr noalias %c, i64 %n) {
91+
; NO-ZVFBFMIN-LABEL: define void @vfwmaccbf16.vv(
92+
; NO-ZVFBFMIN-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
93+
; NO-ZVFBFMIN-NEXT: [[ENTRY:.*]]:
94+
; NO-ZVFBFMIN-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 8
95+
; NO-ZVFBFMIN-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
96+
; NO-ZVFBFMIN: [[VECTOR_PH]]:
97+
; NO-ZVFBFMIN-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 8
98+
; NO-ZVFBFMIN-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
99+
; NO-ZVFBFMIN-NEXT: br label %[[VECTOR_BODY:.*]]
100+
; NO-ZVFBFMIN: [[VECTOR_BODY]]:
101+
; NO-ZVFBFMIN-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
102+
; NO-ZVFBFMIN-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0
103+
; NO-ZVFBFMIN-NEXT: [[TMP1:%.*]] = getelementptr bfloat, ptr [[A]], i64 [[TMP0]]
104+
; NO-ZVFBFMIN-NEXT: [[TMP2:%.*]] = getelementptr bfloat, ptr [[B]], i64 [[TMP0]]
105+
; NO-ZVFBFMIN-NEXT: [[TMP3:%.*]] = getelementptr float, ptr [[C]], i64 [[TMP0]]
106+
; NO-ZVFBFMIN-NEXT: [[TMP4:%.*]] = getelementptr bfloat, ptr [[TMP1]], i32 0
107+
; NO-ZVFBFMIN-NEXT: [[WIDE_LOAD:%.*]] = load <8 x bfloat>, ptr [[TMP4]], align 2
108+
; NO-ZVFBFMIN-NEXT: [[TMP5:%.*]] = getelementptr bfloat, ptr [[TMP2]], i32 0
109+
; NO-ZVFBFMIN-NEXT: [[WIDE_LOAD1:%.*]] = load <8 x bfloat>, ptr [[TMP5]], align 2
110+
; NO-ZVFBFMIN-NEXT: [[TMP6:%.*]] = getelementptr float, ptr [[TMP3]], i32 0
111+
; NO-ZVFBFMIN-NEXT: [[WIDE_LOAD2:%.*]] = load <8 x float>, ptr [[TMP6]], align 4
112+
; NO-ZVFBFMIN-NEXT: [[TMP7:%.*]] = fpext <8 x bfloat> [[WIDE_LOAD]] to <8 x float>
113+
; NO-ZVFBFMIN-NEXT: [[TMP8:%.*]] = fpext <8 x bfloat> [[WIDE_LOAD1]] to <8 x float>
114+
; NO-ZVFBFMIN-NEXT: [[TMP9:%.*]] = call <8 x float> @llvm.fmuladd.v8f32(<8 x float> [[TMP7]], <8 x float> [[TMP8]], <8 x float> [[WIDE_LOAD2]])
115+
; NO-ZVFBFMIN-NEXT: store <8 x float> [[TMP9]], ptr [[TMP6]], align 4
116+
; NO-ZVFBFMIN-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
117+
; NO-ZVFBFMIN-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
118+
; NO-ZVFBFMIN-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
119+
; NO-ZVFBFMIN: [[MIDDLE_BLOCK]]:
120+
; NO-ZVFBFMIN-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
121+
; NO-ZVFBFMIN-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
122+
; NO-ZVFBFMIN: [[SCALAR_PH]]:
123+
; NO-ZVFBFMIN-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
124+
; NO-ZVFBFMIN-NEXT: br label %[[LOOP:.*]]
125+
; NO-ZVFBFMIN: [[LOOP]]:
126+
; NO-ZVFBFMIN-NEXT: [[I:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[I_NEXT:%.*]], %[[LOOP]] ]
127+
; NO-ZVFBFMIN-NEXT: [[A_GEP:%.*]] = getelementptr bfloat, ptr [[A]], i64 [[I]]
128+
; NO-ZVFBFMIN-NEXT: [[B_GEP:%.*]] = getelementptr bfloat, ptr [[B]], i64 [[I]]
129+
; NO-ZVFBFMIN-NEXT: [[C_GEP:%.*]] = getelementptr float, ptr [[C]], i64 [[I]]
130+
; NO-ZVFBFMIN-NEXT: [[X:%.*]] = load bfloat, ptr [[A_GEP]], align 2
131+
; NO-ZVFBFMIN-NEXT: [[Y:%.*]] = load bfloat, ptr [[B_GEP]], align 2
132+
; NO-ZVFBFMIN-NEXT: [[Z:%.*]] = load float, ptr [[C_GEP]], align 4
133+
; NO-ZVFBFMIN-NEXT: [[X_EXT:%.*]] = fpext bfloat [[X]] to float
134+
; NO-ZVFBFMIN-NEXT: [[Y_EXT:%.*]] = fpext bfloat [[Y]] to float
135+
; NO-ZVFBFMIN-NEXT: [[FMULADD:%.*]] = call float @llvm.fmuladd.f32(float [[X_EXT]], float [[Y_EXT]], float [[Z]])
136+
; NO-ZVFBFMIN-NEXT: store float [[FMULADD]], ptr [[C_GEP]], align 4
137+
; NO-ZVFBFMIN-NEXT: [[I_NEXT]] = add i64 [[I]], 1
138+
; NO-ZVFBFMIN-NEXT: [[DONE:%.*]] = icmp eq i64 [[I_NEXT]], [[N]]
139+
; NO-ZVFBFMIN-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
140+
; NO-ZVFBFMIN: [[EXIT]]:
141+
; NO-ZVFBFMIN-NEXT: ret void
142+
;
143+
; ZVFBFMIN-LABEL: define void @vfwmaccbf16.vv(
144+
; ZVFBFMIN-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
145+
; ZVFBFMIN-NEXT: [[ENTRY:.*]]:
146+
; ZVFBFMIN-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
147+
; ZVFBFMIN-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], 4
148+
; ZVFBFMIN-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], [[TMP1]]
149+
; ZVFBFMIN-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
150+
; ZVFBFMIN: [[VECTOR_PH]]:
151+
; ZVFBFMIN-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
152+
; ZVFBFMIN-NEXT: [[TMP3:%.*]] = mul i64 [[TMP2]], 4
153+
; ZVFBFMIN-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP3]]
154+
; ZVFBFMIN-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
155+
; ZVFBFMIN-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()
156+
; ZVFBFMIN-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 4
157+
; ZVFBFMIN-NEXT: br label %[[VECTOR_BODY:.*]]
158+
; ZVFBFMIN: [[VECTOR_BODY]]:
159+
; ZVFBFMIN-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
160+
; ZVFBFMIN-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], 0
161+
; ZVFBFMIN-NEXT: [[TMP7:%.*]] = getelementptr bfloat, ptr [[A]], i64 [[TMP6]]
162+
; ZVFBFMIN-NEXT: [[TMP8:%.*]] = getelementptr bfloat, ptr [[B]], i64 [[TMP6]]
163+
; ZVFBFMIN-NEXT: [[TMP9:%.*]] = getelementptr float, ptr [[C]], i64 [[TMP6]]
164+
; ZVFBFMIN-NEXT: [[TMP10:%.*]] = getelementptr bfloat, ptr [[TMP7]], i32 0
165+
; ZVFBFMIN-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x bfloat>, ptr [[TMP10]], align 2
166+
; ZVFBFMIN-NEXT: [[TMP11:%.*]] = getelementptr bfloat, ptr [[TMP8]], i32 0
167+
; ZVFBFMIN-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 4 x bfloat>, ptr [[TMP11]], align 2
168+
; ZVFBFMIN-NEXT: [[TMP12:%.*]] = getelementptr float, ptr [[TMP9]], i32 0
169+
; ZVFBFMIN-NEXT: [[WIDE_LOAD2:%.*]] = load <vscale x 4 x float>, ptr [[TMP12]], align 4
170+
; ZVFBFMIN-NEXT: [[TMP13:%.*]] = fpext <vscale x 4 x bfloat> [[WIDE_LOAD]] to <vscale x 4 x float>
171+
; ZVFBFMIN-NEXT: [[TMP14:%.*]] = fpext <vscale x 4 x bfloat> [[WIDE_LOAD1]] to <vscale x 4 x float>
172+
; ZVFBFMIN-NEXT: [[TMP15:%.*]] = call <vscale x 4 x float> @llvm.fmuladd.nxv4f32(<vscale x 4 x float> [[TMP13]], <vscale x 4 x float> [[TMP14]], <vscale x 4 x float> [[WIDE_LOAD2]])
173+
; ZVFBFMIN-NEXT: store <vscale x 4 x float> [[TMP15]], ptr [[TMP12]], align 4
174+
; ZVFBFMIN-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP5]]
175+
; ZVFBFMIN-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
176+
; ZVFBFMIN-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
177+
; ZVFBFMIN: [[MIDDLE_BLOCK]]:
178+
; ZVFBFMIN-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
179+
; ZVFBFMIN-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
180+
; ZVFBFMIN: [[SCALAR_PH]]:
181+
; ZVFBFMIN-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
182+
; ZVFBFMIN-NEXT: br label %[[LOOP:.*]]
183+
; ZVFBFMIN: [[LOOP]]:
184+
; ZVFBFMIN-NEXT: [[I:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[I_NEXT:%.*]], %[[LOOP]] ]
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; ZVFBFMIN-NEXT: [[A_GEP:%.*]] = getelementptr bfloat, ptr [[A]], i64 [[I]]
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; ZVFBFMIN-NEXT: [[B_GEP:%.*]] = getelementptr bfloat, ptr [[B]], i64 [[I]]
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; ZVFBFMIN-NEXT: [[C_GEP:%.*]] = getelementptr float, ptr [[C]], i64 [[I]]
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; ZVFBFMIN-NEXT: [[X:%.*]] = load bfloat, ptr [[A_GEP]], align 2
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; ZVFBFMIN-NEXT: [[Y:%.*]] = load bfloat, ptr [[B_GEP]], align 2
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; ZVFBFMIN-NEXT: [[Z:%.*]] = load float, ptr [[C_GEP]], align 4
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; ZVFBFMIN-NEXT: [[X_EXT:%.*]] = fpext bfloat [[X]] to float
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; ZVFBFMIN-NEXT: [[Y_EXT:%.*]] = fpext bfloat [[Y]] to float
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; ZVFBFMIN-NEXT: [[FMULADD:%.*]] = call float @llvm.fmuladd.f32(float [[X_EXT]], float [[Y_EXT]], float [[Z]])
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; ZVFBFMIN-NEXT: store float [[FMULADD]], ptr [[C_GEP]], align 4
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; ZVFBFMIN-NEXT: [[I_NEXT]] = add i64 [[I]], 1
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; ZVFBFMIN-NEXT: [[DONE:%.*]] = icmp eq i64 [[I_NEXT]], [[N]]
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; ZVFBFMIN-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
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; ZVFBFMIN: [[EXIT]]:
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; ZVFBFMIN-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%i = phi i64 [0, %entry], [%i.next, %loop]
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%a.gep = getelementptr bfloat, ptr %a, i64 %i
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%b.gep = getelementptr bfloat, ptr %b, i64 %i
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%c.gep = getelementptr float, ptr %c, i64 %i
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%x = load bfloat, ptr %a.gep
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%y = load bfloat, ptr %b.gep
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%z = load float, ptr %c.gep
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%x.ext = fpext bfloat %x to float
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%y.ext = fpext bfloat %y to float
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%fmuladd = call float @llvm.fmuladd.f32(float %x.ext, float %y.ext, float %z)
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store float %fmuladd, ptr %c.gep
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%i.next = add i64 %i, 1
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%done = icmp eq i64 %i.next, %n
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br i1 %done, label %exit, label %loop
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exit:
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ret void
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}
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;.
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; NO-ZVFBFMIN: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
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; NO-ZVFBFMIN: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
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; NO-ZVFBFMIN: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
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; NO-ZVFBFMIN: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
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;.
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; ZVFBFMIN: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
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; ZVFBFMIN: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
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; ZVFBFMIN: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
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; ZVFBFMIN: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
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; ZVFBFMIN: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
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; ZVFBFMIN: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}
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;.

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