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[CodeGen] Make use of MachineInstrBuilder::getReg
Reviewers: arsenm Subscribers: wdng, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D73262
1 parent d6a97b0 commit b482e1b

13 files changed

+159
-163
lines changed

‎llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -129,7 +129,7 @@ CSEMIRBuilder::generateCopiesIfRequired(ArrayRef<DstOp> DstOps,
129129
if (DstOps.size() == 1) {
130130
const DstOp &Op = DstOps[0];
131131
if (Op.getDstOpKind() == DstOp::DstType::Ty_Reg)
132-
return buildCopy(Op.getReg(), MIB->getOperand(0).getReg());
132+
return buildCopy(Op.getReg(), MIB.getReg(0));
133133
}
134134
return MIB;
135135
}

‎llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -469,7 +469,7 @@ Register CallLowering::ValueHandler::extendRegister(Register ValReg,
469469
return ValReg;
470470
case CCValAssign::AExt: {
471471
auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg);
472-
return MIB->getOperand(0).getReg();
472+
return MIB.getReg(0);
473473
}
474474
case CCValAssign::SExt: {
475475
Register NewReg = MRI.createGenericVirtualRegister(LocTy);

‎llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1916,7 +1916,7 @@ bool IRTranslator::translateExtractElement(const User &U,
19161916
Idx = getOrCreateVReg(*U.getOperand(1));
19171917
if (MRI->getType(Idx).getSizeInBits() != PreferredVecIdxWidth) {
19181918
const LLT &VecIdxTy = LLT::scalar(PreferredVecIdxWidth);
1919-
Idx = MIRBuilder.buildSExtOrTrunc(VecIdxTy, Idx)->getOperand(0).getReg();
1919+
Idx = MIRBuilder.buildSExtOrTrunc(VecIdxTy, Idx).getReg(0);
19201920
}
19211921
MIRBuilder.buildExtractVectorElement(Res, Val, Idx);
19221922
return true;

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 15 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -751,7 +751,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
751751
SmallVector<Register, 2> DstRegs;
752752
for (int i = 0; i < NumParts; ++i)
753753
DstRegs.push_back(
754-
MIRBuilder.buildUndef(NarrowTy)->getOperand(0).getReg());
754+
MIRBuilder.buildUndef(NarrowTy).getReg(0));
755755

756756
Register DstReg = MI.getOperand(0).getReg();
757757
if(MRI.getType(DstReg).isVector())
@@ -1091,7 +1091,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
10911091
// sign-extending the dst.
10921092
MachineOperand &MO1 = MI.getOperand(1);
10931093
auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1);
1094-
MO1.setReg(TruncMIB->getOperand(0).getReg());
1094+
MO1.setReg(TruncMIB.getReg(0));
10951095

10961096
MachineOperand &MO2 = MI.getOperand(0);
10971097
Register DstExt = MRI.createGenericVirtualRegister(NarrowTy);
@@ -1127,8 +1127,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
11271127

11281128
Register AshrCstReg =
11291129
MIRBuilder.buildConstant(NarrowTy, NarrowTy.getScalarSizeInBits() - 1)
1130-
->getOperand(0)
1131-
.getReg();
1130+
.getReg(0);
11321131
Register FullExtensionReg = 0;
11331132
Register PartialExtensionReg = 0;
11341133

@@ -1145,17 +1144,15 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
11451144
}
11461145
DstRegs.push_back(
11471146
MIRBuilder.buildAShr(NarrowTy, PartialExtensionReg, AshrCstReg)
1148-
->getOperand(0)
1149-
.getReg());
1147+
.getReg(0));
11501148
FullExtensionReg = DstRegs.back();
11511149
} else {
11521150
DstRegs.push_back(
11531151
MIRBuilder
11541152
.buildInstr(
11551153
TargetOpcode::G_SEXT_INREG, {NarrowTy},
11561154
{SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()})
1157-
->getOperand(0)
1158-
.getReg());
1155+
.getReg(0));
11591156
PartialExtensionReg = DstRegs.back();
11601157
}
11611158
}
@@ -1195,14 +1192,14 @@ void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
11951192
unsigned OpIdx, unsigned ExtOpcode) {
11961193
MachineOperand &MO = MI.getOperand(OpIdx);
11971194
auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO});
1198-
MO.setReg(ExtB->getOperand(0).getReg());
1195+
MO.setReg(ExtB.getReg(0));
11991196
}
12001197

12011198
void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy,
12021199
unsigned OpIdx) {
12031200
MachineOperand &MO = MI.getOperand(OpIdx);
12041201
auto ExtB = MIRBuilder.buildTrunc(NarrowTy, MO);
1205-
MO.setReg(ExtB->getOperand(0).getReg());
1202+
MO.setReg(ExtB.getReg(0));
12061203
}
12071204

12081205
void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
@@ -1415,7 +1412,7 @@ LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx,
14151412

14161413
Observer.changingInstr(MI);
14171414

1418-
MI.getOperand(NumDst).setReg(WideSrc->getOperand(0).getReg());
1415+
MI.getOperand(NumDst).setReg(WideSrc.getReg(0));
14191416
for (unsigned I = 0; I != NumDst; ++I)
14201417
widenScalarDst(MI, WideTy, I);
14211418

@@ -2145,7 +2142,7 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
21452142
*cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
21462143
auto Zero = MIRBuilder.buildFConstant(Ty, ZeroForNegation);
21472144
Register SubByReg = MI.getOperand(1).getReg();
2148-
Register ZeroReg = Zero->getOperand(0).getReg();
2145+
Register ZeroReg = Zero.getReg(0);
21492146
MIRBuilder.buildFSub(Res, ZeroReg, SubByReg, MI.getFlags());
21502147
MI.eraseFromParent();
21512148
return Legalized;
@@ -3769,14 +3766,14 @@ LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx,
37693766
for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
37703767
auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
37713768
{Src0Regs[I], Src1Regs[I]});
3772-
DstRegs.push_back(Inst->getOperand(0).getReg());
3769+
DstRegs.push_back(Inst.getReg(0));
37733770
}
37743771

37753772
for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
37763773
auto Inst = MIRBuilder.buildInstr(
37773774
MI.getOpcode(),
37783775
{LeftoverTy}, {Src0LeftoverRegs[I], Src1LeftoverRegs[I]});
3779-
DstLeftoverRegs.push_back(Inst->getOperand(0).getReg());
3776+
DstLeftoverRegs.push_back(Inst.getReg(0));
37803777
}
37813778

37823779
insertParts(DstReg, DstTy, NarrowTy, DstRegs,
@@ -3836,13 +3833,13 @@ LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx,
38363833
for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
38373834
auto Select = MIRBuilder.buildSelect(NarrowTy,
38383835
CondReg, Src1Regs[I], Src2Regs[I]);
3839-
DstRegs.push_back(Select->getOperand(0).getReg());
3836+
DstRegs.push_back(Select.getReg(0));
38403837
}
38413838

38423839
for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
38433840
auto Select = MIRBuilder.buildSelect(
38443841
LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]);
3845-
DstLeftoverRegs.push_back(Select->getOperand(0).getReg());
3842+
DstLeftoverRegs.push_back(Select.getReg(0));
38463843
}
38473844

38483845
insertParts(DstReg, DstTy, NarrowTy, DstRegs,
@@ -3901,7 +3898,7 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
39013898
auto MIBShiftAmt = MIRBuilder.buildConstant(Ty, 1ULL << i);
39023899
auto MIBOp =
39033900
MIRBuilder.buildOr(Ty, Op, MIRBuilder.buildLShr(Ty, Op, MIBShiftAmt));
3904-
Op = MIBOp->getOperand(0).getReg();
3901+
Op = MIBOp.getReg(0);
39053902
}
39063903
auto MIBPop = MIRBuilder.buildCTPOP(Ty, Op);
39073904
MIRBuilder.buildSub(MI.getOperand(0), MIRBuilder.buildConstant(Ty, Len),
@@ -3948,7 +3945,7 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
39483945
return Legalized;
39493946
}
39503947
MI.setDesc(TII.get(TargetOpcode::G_CTPOP));
3951-
MI.getOperand(1).setReg(MIBTmp->getOperand(0).getReg());
3948+
MI.getOperand(1).setReg(MIBTmp.getReg(0));
39523949
return Legalized;
39533950
}
39543951
}

‎llvm/lib/CodeGen/MachineSSAUpdater.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -204,7 +204,7 @@ unsigned MachineSSAUpdater::GetValueInMiddleOfBlock(MachineBasicBlock *BB) {
204204
if (InsertedPHIs) InsertedPHIs->push_back(InsertedPHI);
205205

206206
LLVM_DEBUG(dbgs() << " Inserted PHI: " << *InsertedPHI << "\n");
207-
return InsertedPHI->getOperand(0).getReg();
207+
return InsertedPHI.getReg(0);
208208
}
209209

210210
static

‎llvm/lib/Target/AArch64/AArch64CallLowering.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -178,8 +178,7 @@ struct OutgoingArgHandler : public CallLowering::ValueHandler {
178178
if (VA.getLocInfo() == CCValAssign::LocInfo::AExt) {
179179
Size = VA.getLocVT().getSizeInBits() / 8;
180180
ValVReg = MIRBuilder.buildAnyExt(LLT::scalar(Size * 8), ValVReg)
181-
->getOperand(0)
182-
.getReg();
181+
.getReg(0);
183182
}
184183
auto MMO = MIRBuilder.getMF().getMachineMemOperand(
185184
MPO, MachineMemOperand::MOStore, Size, 1);

‎llvm/lib/Target/ARM/ARMInstructionSelector.cpp

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -239,17 +239,17 @@ static bool selectMergeValues(MachineInstrBuilder &MIB,
239239

240240
// We only support G_MERGE_VALUES as a way to stick together two scalar GPRs
241241
// into one DPR.
242-
Register VReg0 = MIB->getOperand(0).getReg();
242+
Register VReg0 = MIB.getReg(0);
243243
(void)VReg0;
244244
assert(MRI.getType(VReg0).getSizeInBits() == 64 &&
245245
RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID &&
246246
"Unsupported operand for G_MERGE_VALUES");
247-
Register VReg1 = MIB->getOperand(1).getReg();
247+
Register VReg1 = MIB.getReg(1);
248248
(void)VReg1;
249249
assert(MRI.getType(VReg1).getSizeInBits() == 32 &&
250250
RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
251251
"Unsupported operand for G_MERGE_VALUES");
252-
Register VReg2 = MIB->getOperand(2).getReg();
252+
Register VReg2 = MIB.getReg(2);
253253
(void)VReg2;
254254
assert(MRI.getType(VReg2).getSizeInBits() == 32 &&
255255
RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID &&
@@ -271,17 +271,17 @@ static bool selectUnmergeValues(MachineInstrBuilder &MIB,
271271

272272
// We only support G_UNMERGE_VALUES as a way to break up one DPR into two
273273
// GPRs.
274-
Register VReg0 = MIB->getOperand(0).getReg();
274+
Register VReg0 = MIB.getReg(0);
275275
(void)VReg0;
276276
assert(MRI.getType(VReg0).getSizeInBits() == 32 &&
277277
RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID &&
278278
"Unsupported operand for G_UNMERGE_VALUES");
279-
Register VReg1 = MIB->getOperand(1).getReg();
279+
Register VReg1 = MIB.getReg(1);
280280
(void)VReg1;
281281
assert(MRI.getType(VReg1).getSizeInBits() == 32 &&
282282
RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
283283
"Unsupported operand for G_UNMERGE_VALUES");
284-
Register VReg2 = MIB->getOperand(2).getReg();
284+
Register VReg2 = MIB.getReg(2);
285285
(void)VReg2;
286286
assert(MRI.getType(VReg2).getSizeInBits() == 64 &&
287287
RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID &&
@@ -530,7 +530,7 @@ bool ARMInstructionSelector::selectCmp(CmpConstants Helper,
530530
MachineRegisterInfo &MRI) const {
531531
const InsertInfo I(MIB);
532532

533-
auto ResReg = MIB->getOperand(0).getReg();
533+
auto ResReg = MIB.getReg(0);
534534
if (!validReg(MRI, ResReg, 1, ARM::GPRRegBankID))
535535
return false;
536536

@@ -542,8 +542,8 @@ bool ARMInstructionSelector::selectCmp(CmpConstants Helper,
542542
return true;
543543
}
544544

545-
auto LHSReg = MIB->getOperand(2).getReg();
546-
auto RHSReg = MIB->getOperand(3).getReg();
545+
auto LHSReg = MIB.getReg(2);
546+
auto RHSReg = MIB.getReg(3);
547547
if (!validOpRegPair(MRI, LHSReg, RHSReg, Helper.OperandSize,
548548
Helper.OperandRegBankID))
549549
return false;
@@ -687,7 +687,7 @@ bool ARMInstructionSelector::selectGlobal(MachineInstrBuilder &MIB,
687687

688688
if (Indirect) {
689689
if (!UseOpcodeThatLoads) {
690-
auto ResultReg = MIB->getOperand(0).getReg();
690+
auto ResultReg = MIB.getReg(0);
691691
auto AddressReg = MRI.createVirtualRegister(&ARM::GPRRegClass);
692692

693693
MIB->getOperand(0).setReg(AddressReg);
@@ -773,7 +773,7 @@ bool ARMInstructionSelector::selectSelect(MachineInstrBuilder &MIB,
773773
auto &DbgLoc = MIB->getDebugLoc();
774774

775775
// Compare the condition to 1.
776-
auto CondReg = MIB->getOperand(1).getReg();
776+
auto CondReg = MIB.getReg(1);
777777
assert(validReg(MRI, CondReg, 1, ARM::GPRRegBankID) &&
778778
"Unsupported types for select operation");
779779
auto CmpI = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(Opcodes.TSTri))
@@ -785,9 +785,9 @@ bool ARMInstructionSelector::selectSelect(MachineInstrBuilder &MIB,
785785

786786
// Move a value into the result register based on the result of the
787787
// comparison.
788-
auto ResReg = MIB->getOperand(0).getReg();
789-
auto TrueReg = MIB->getOperand(2).getReg();
790-
auto FalseReg = MIB->getOperand(3).getReg();
788+
auto ResReg = MIB.getReg(0);
789+
auto TrueReg = MIB.getReg(2);
790+
auto FalseReg = MIB.getReg(3);
791791
assert(validOpRegPair(MRI, ResReg, TrueReg, 32, ARM::GPRRegBankID) &&
792792
validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) &&
793793
"Unsupported types for select operation");

‎llvm/lib/Target/X86/X86CallLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -139,7 +139,7 @@ struct OutgoingValueHandler : public CallLowering::ValueHandler {
139139
if (PhysRegSize > ValSize && LocSize == ValSize) {
140140
assert((PhysRegSize == 128 || PhysRegSize == 80) && "We expect that to be 128 bit");
141141
auto MIB = MIRBuilder.buildAnyExt(LLT::scalar(PhysRegSize), ValVReg);
142-
ExtReg = MIB->getOperand(0).getReg();
142+
ExtReg = MIB.getReg(0);
143143
} else
144144
ExtReg = extendRegister(ValVReg, VA);
145145

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