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Merge commit 'e9dcc15f514a' from llvm.org/release/17.x into stable/20230725
2 parents 9b7dff1 + e9dcc15 commit b53e4bf

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‎llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

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@@ -212,6 +212,30 @@ bool AArch64TTIImpl::areInlineCompatible(const Function *Caller,
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return (CallerBits & CalleeBits) == CalleeBits;
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}
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bool AArch64TTIImpl::areTypesABICompatible(
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const Function *Caller, const Function *Callee,
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const ArrayRef<Type *> &Types) const {
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if (!BaseT::areTypesABICompatible(Caller, Callee, Types))
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return false;
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// We need to ensure that argument promotion does not attempt to promote
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// pointers to fixed-length vector types larger than 128 bits like
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// <8 x float> (and pointers to aggregate types which have such fixed-length
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// vector type members) into the values of the pointees. Such vector types
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// are used for SVE VLS but there is no ABI for SVE VLS arguments and the
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// backend cannot lower such value arguments. The 128-bit fixed-length SVE
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// types can be safely treated as 128-bit NEON types and they cannot be
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// distinguished in IR.
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if (ST->useSVEForFixedLengthVectors() && llvm::any_of(Types, [](Type *Ty) {
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auto FVTy = dyn_cast<FixedVectorType>(Ty);
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return FVTy &&
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FVTy->getScalarSizeInBits() * FVTy->getNumElements() > 128;
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}))
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return false;
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return true;
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}
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bool AArch64TTIImpl::shouldMaximizeVectorBandwidth(
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TargetTransformInfo::RegisterKind K) const {
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assert(K != TargetTransformInfo::RGK_Scalar);

‎llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h

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@@ -77,6 +77,9 @@ class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> {
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bool areInlineCompatible(const Function *Caller,
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const Function *Callee) const;
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bool areTypesABICompatible(const Function *Caller, const Function *Callee,
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const ArrayRef<Type *> &Types) const;
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/// \name Scalar TTI Implementations
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/// @{
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‎llvm/test/CodeGen/AArch64/arg_promotion.ll

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@@ -0,0 +1,190 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -passes=argpromotion -mtriple=aarch64-unknwon-linux-gnu < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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; Don't promote a vector pointer argument when the pointee type size is greater
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; than 128 bits.
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define dso_local void @caller_8xi32(ptr noalias %src, ptr noalias %dst) #0 {
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; CHECK-LABEL: define dso_local void @caller_8xi32(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: call fastcc void @callee_8xi32(ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]])
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; CHECK-NEXT: ret void
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;
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entry:
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call fastcc void @callee_8xi32(ptr noalias %src, ptr noalias %dst)
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ret void
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}
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define internal fastcc void @callee_8xi32(ptr noalias %src, ptr noalias %dst) #0 {
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; CHECK-LABEL: define internal fastcc void @callee_8xi32(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i32>, ptr [[SRC:%.*]], align 16
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; CHECK-NEXT: store <8 x i32> [[TMP0]], ptr [[DST:%.*]], align 16
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; CHECK-NEXT: ret void
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;
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entry:
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%0 = load <8 x i32>, ptr %src, align 16
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store <8 x i32> %0, ptr %dst, align 16
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ret void
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}
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; Promote a vector pointer argument when the pointee type size is 128 bits or
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; less.
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define dso_local void @caller_4xi32(ptr noalias %src, ptr noalias %dst) #1 {
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; CHECK-LABEL: define dso_local void @caller_4xi32(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[SRC_VAL:%.*]] = load <4 x i32>, ptr [[SRC:%.*]], align 16
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; CHECK-NEXT: call fastcc void @callee_4xi32(<4 x i32> [[SRC_VAL]], ptr noalias [[DST:%.*]])
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; CHECK-NEXT: ret void
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;
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entry:
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call fastcc void @callee_4xi32(ptr noalias %src, ptr noalias %dst)
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ret void
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}
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define internal fastcc void @callee_4xi32(ptr noalias %src, ptr noalias %dst) #1 {
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; CHECK-LABEL: define internal fastcc void @callee_4xi32(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: store <4 x i32> [[SRC_0_VAL:%.*]], ptr [[DST:%.*]], align 16
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; CHECK-NEXT: ret void
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;
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entry:
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%0 = load <4 x i32>, ptr %src, align 16
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store <4 x i32> %0, ptr %dst, align 16
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ret void
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}
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; A scalar pointer argument is promoted even when the pointee type size is
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; greater than 128 bits.
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define dso_local void @caller_i256(ptr noalias %src, ptr noalias %dst) #0 {
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; CHECK-LABEL: define dso_local void @caller_i256(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[SRC_VAL:%.*]] = load i256, ptr [[SRC:%.*]], align 16
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; CHECK-NEXT: call fastcc void @callee_i256(i256 [[SRC_VAL]], ptr noalias [[DST:%.*]])
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; CHECK-NEXT: ret void
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;
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entry:
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call fastcc void @callee_i256(ptr noalias %src, ptr noalias %dst)
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ret void
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}
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define internal fastcc void @callee_i256(ptr noalias %src, ptr noalias %dst) #0 {
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; CHECK-LABEL: define internal fastcc void @callee_i256(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: store i256 [[SRC_0_VAL:%.*]], ptr [[DST:%.*]], align 16
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; CHECK-NEXT: ret void
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;
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entry:
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%0 = load i256, ptr %src, align 16
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store i256 %0, ptr %dst, align 16
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ret void
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}
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; A scalable vector pointer argument is not a target of ArgumentPromotionPass.
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define dso_local void @caller_nx4xi32(ptr noalias %src, ptr noalias %dst) #2 {
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; CHECK-LABEL: define dso_local void @caller_nx4xi32(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: call fastcc void @callee_nx4xi32(ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]])
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; CHECK-NEXT: ret void
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;
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entry:
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call fastcc void @callee_nx4xi32(ptr noalias %src, ptr noalias %dst)
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ret void
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}
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define internal fastcc void @callee_nx4xi32(ptr noalias %src, ptr noalias %dst) #2 {
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; CHECK-LABEL: define internal fastcc void @callee_nx4xi32(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load <vscale x 4 x i32>, ptr [[SRC:%.*]], align 16
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; CHECK-NEXT: store <vscale x 4 x i32> [[TMP0]], ptr [[DST:%.*]], align 16
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; CHECK-NEXT: ret void
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;
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entry:
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%0 = load <vscale x 4 x i32>, ptr %src, align 16
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store <vscale x 4 x i32> %0, ptr %dst, align 16
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ret void
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}
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; Don't promote a structure pointer argument when the pointee vector member
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; type size is greater than 128 bits.
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%struct_8xi32 = type { <8 x i32>, <8 x i32> }
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define dso_local void @caller_struct8xi32(ptr noalias %src, ptr noalias %dst) #0 {
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; CHECK-LABEL: define dso_local void @caller_struct8xi32(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: call fastcc void @callee_struct8xi32(ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]])
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; CHECK-NEXT: ret void
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;
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entry:
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call fastcc void @callee_struct8xi32(ptr noalias %src, ptr noalias %dst)
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ret void
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}
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define internal fastcc void @callee_struct8xi32(ptr noalias %src, ptr noalias %dst) #0 {
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; CHECK-LABEL: define internal fastcc void @callee_struct8xi32(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i32>, ptr [[SRC:%.*]], align 16
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; CHECK-NEXT: store <8 x i32> [[TMP0]], ptr [[DST:%.*]], align 16
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; CHECK-NEXT: [[SRC2:%.*]] = getelementptr inbounds [[STRUCT_8XI32:%.*]], ptr [[SRC]], i64 0, i32 1
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; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr [[SRC2]], align 16
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; CHECK-NEXT: [[DST2:%.*]] = getelementptr inbounds [[STRUCT_8XI32]], ptr [[DST]], i64 0, i32 1
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; CHECK-NEXT: store <8 x i32> [[TMP1]], ptr [[DST2]], align 16
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; CHECK-NEXT: ret void
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;
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entry:
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%0 = load <8 x i32>, ptr %src, align 16
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store <8 x i32> %0, ptr %dst, align 16
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%src2 = getelementptr inbounds %struct_8xi32, ptr %src, i64 0, i32 1
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%1 = load <8 x i32>, ptr %src2, align 16
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%dst2 = getelementptr inbounds %struct_8xi32, ptr %dst, i64 0, i32 1
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store <8 x i32> %1, ptr %dst2, align 16
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ret void
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}
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; Promote a structure pointer argument when the pointee vector member type size
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; is 128 bits or less.
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%struct_4xi32 = type { <4 x i32>, <4 x i32> }
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define dso_local void @caller_struct4xi32(ptr noalias %src, ptr noalias %dst) #1 {
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; CHECK-LABEL: define dso_local void @caller_struct4xi32(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[SRC_VAL:%.*]] = load <4 x i32>, ptr [[SRC:%.*]], align 16
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; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[SRC]], i64 16
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; CHECK-NEXT: [[SRC_VAL1:%.*]] = load <4 x i32>, ptr [[TMP0]], align 16
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; CHECK-NEXT: call fastcc void @callee_struct4xi32(<4 x i32> [[SRC_VAL]], <4 x i32> [[SRC_VAL1]], ptr noalias [[DST:%.*]])
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; CHECK-NEXT: ret void
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;
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entry:
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call fastcc void @callee_struct4xi32(ptr noalias %src, ptr noalias %dst)
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ret void
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}
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define internal fastcc void @callee_struct4xi32(ptr noalias %src, ptr noalias %dst) #1 {
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; CHECK-LABEL: define internal fastcc void @callee_struct4xi32(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: store <4 x i32> [[SRC_0_VAL:%.*]], ptr [[DST:%.*]], align 16
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; CHECK-NEXT: [[DST2:%.*]] = getelementptr inbounds [[STRUCT_4XI32:%.*]], ptr [[DST]], i64 0, i32 1
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; CHECK-NEXT: store <4 x i32> [[SRC_16_VAL:%.*]], ptr [[DST2]], align 16
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; CHECK-NEXT: ret void
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;
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entry:
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%0 = load <4 x i32>, ptr %src, align 16
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store <4 x i32> %0, ptr %dst, align 16
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%src2 = getelementptr inbounds %struct_4xi32, ptr %src, i64 0, i32 1
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%1 = load <4 x i32>, ptr %src2, align 16
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%dst2 = getelementptr inbounds %struct_4xi32, ptr %dst, i64 0, i32 1
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store <4 x i32> %1, ptr %dst2, align 16
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ret void
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}
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attributes #0 = { noinline vscale_range(2,2) "target-features"="+v8.2a,+neon,+sve" }
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attributes #1 = { noinline vscale_range(1,1) "target-features"="+v8.2a,+neon,+sve" }
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attributes #2 = { noinline "target-features"="+v8.2a,+neon,+sve" }

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