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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py |
| 2 | +; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s |
| 3 | + |
| 4 | +declare void @sideeffect0() |
| 5 | +declare void @sideeffect1() |
| 6 | +declare void @sideeffect2() |
| 7 | + |
| 8 | +define i32 @unknown(i1 %c, i32 %a, i32 %b) { |
| 9 | +; CHECK-LABEL: @unknown( |
| 10 | +; CHECK-NEXT: entry: |
| 11 | +; CHECK-NEXT: call void @sideeffect0() |
| 12 | +; CHECK-NEXT: br i1 [[C:%.*]], label [[DISPATCH:%.*]], label [[END:%.*]] |
| 13 | +; CHECK: dispatch: |
| 14 | +; CHECK-NEXT: call void @sideeffect1() |
| 15 | +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]] |
| 16 | +; CHECK-NEXT: [[VAL:%.*]] = add i32 [[A]], [[B]] |
| 17 | +; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[CMP]], i32 [[VAL]], i32 0 |
| 18 | +; CHECK-NEXT: br label [[END]] |
| 19 | +; CHECK: end: |
| 20 | +; CHECK-NEXT: [[RES:%.*]] = phi i32 [ -1, [[ENTRY:%.*]] ], [ [[SPEC_SELECT]], [[DISPATCH]] ] |
| 21 | +; CHECK-NEXT: call void @sideeffect2() |
| 22 | +; CHECK-NEXT: ret i32 [[RES]] |
| 23 | +; |
| 24 | +entry: |
| 25 | + call void @sideeffect0() |
| 26 | + br i1 %c, label %dispatch, label %end |
| 27 | + |
| 28 | +dispatch: |
| 29 | + call void @sideeffect1() |
| 30 | + %cmp = icmp eq i32 %a, %b |
| 31 | + br i1 %cmp, label %cond.true, label %end |
| 32 | + |
| 33 | +cond.true: |
| 34 | + %val = add i32 %a, %b |
| 35 | + br label %end |
| 36 | + |
| 37 | +end: |
| 38 | + %res = phi i32 [ -1, %entry ], [ 0, %dispatch ], [ %val, %cond.true ] |
| 39 | + call void @sideeffect2() |
| 40 | + ret i32 %res |
| 41 | +} |
| 42 | + |
| 43 | +define i32 @predictably_taken(i1 %c, i32 %a, i32 %b) { |
| 44 | +; CHECK-LABEL: @predictably_taken( |
| 45 | +; CHECK-NEXT: entry: |
| 46 | +; CHECK-NEXT: call void @sideeffect0() |
| 47 | +; CHECK-NEXT: br i1 [[C:%.*]], label [[DISPATCH:%.*]], label [[END:%.*]] |
| 48 | +; CHECK: dispatch: |
| 49 | +; CHECK-NEXT: call void @sideeffect1() |
| 50 | +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]] |
| 51 | +; CHECK-NEXT: [[VAL:%.*]] = add i32 [[A]], [[B]] |
| 52 | +; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[CMP]], i32 [[VAL]], i32 0, !prof [[PROF0:![0-9]+]] |
| 53 | +; CHECK-NEXT: br label [[END]] |
| 54 | +; CHECK: end: |
| 55 | +; CHECK-NEXT: [[RES:%.*]] = phi i32 [ -1, [[ENTRY:%.*]] ], [ [[SPEC_SELECT]], [[DISPATCH]] ] |
| 56 | +; CHECK-NEXT: call void @sideeffect2() |
| 57 | +; CHECK-NEXT: ret i32 [[RES]] |
| 58 | +; |
| 59 | +entry: |
| 60 | + call void @sideeffect0() |
| 61 | + br i1 %c, label %dispatch, label %end |
| 62 | + |
| 63 | +dispatch: |
| 64 | + call void @sideeffect1() |
| 65 | + %cmp = icmp eq i32 %a, %b |
| 66 | + br i1 %cmp, label %cond.true, label %end, !prof !0 ; likely branches to %cond.true |
| 67 | + |
| 68 | +cond.true: |
| 69 | + %val = add i32 %a, %b |
| 70 | + br label %end |
| 71 | + |
| 72 | +end: |
| 73 | + %res = phi i32 [ -1, %entry ], [ 0, %dispatch ], [ %val, %cond.true ] |
| 74 | + call void @sideeffect2() |
| 75 | + ret i32 %res |
| 76 | +} |
| 77 | + |
| 78 | +define i32 @predictably_nontaken(i1 %c, i32 %a, i32 %b) { |
| 79 | +; CHECK-LABEL: @predictably_nontaken( |
| 80 | +; CHECK-NEXT: entry: |
| 81 | +; CHECK-NEXT: call void @sideeffect0() |
| 82 | +; CHECK-NEXT: br i1 [[C:%.*]], label [[DISPATCH:%.*]], label [[END:%.*]] |
| 83 | +; CHECK: dispatch: |
| 84 | +; CHECK-NEXT: call void @sideeffect1() |
| 85 | +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]] |
| 86 | +; CHECK-NEXT: [[VAL:%.*]] = add i32 [[A]], [[B]] |
| 87 | +; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[CMP]], i32 0, i32 [[VAL]], !prof [[PROF0]] |
| 88 | +; CHECK-NEXT: br label [[END]] |
| 89 | +; CHECK: end: |
| 90 | +; CHECK-NEXT: [[RES:%.*]] = phi i32 [ -1, [[ENTRY:%.*]] ], [ [[SPEC_SELECT]], [[DISPATCH]] ] |
| 91 | +; CHECK-NEXT: call void @sideeffect2() |
| 92 | +; CHECK-NEXT: ret i32 [[RES]] |
| 93 | +; |
| 94 | +entry: |
| 95 | + call void @sideeffect0() |
| 96 | + br i1 %c, label %dispatch, label %end |
| 97 | + |
| 98 | +dispatch: |
| 99 | + call void @sideeffect1() |
| 100 | + %cmp = icmp eq i32 %a, %b |
| 101 | + br i1 %cmp, label %end, label %cond.true, !prof !0 ; likely branches to %end |
| 102 | + |
| 103 | +cond.true: |
| 104 | + %val = add i32 %a, %b |
| 105 | + br label %end |
| 106 | + |
| 107 | +end: |
| 108 | + %res = phi i32 [ -1, %entry ], [ 0, %dispatch ], [ %val, %cond.true ] |
| 109 | + call void @sideeffect2() |
| 110 | + ret i32 %res |
| 111 | +} |
| 112 | + |
| 113 | +define i32 @unpredictable(i1 %c, i32 %a, i32 %b) { |
| 114 | +; CHECK-LABEL: @unpredictable( |
| 115 | +; CHECK-NEXT: entry: |
| 116 | +; CHECK-NEXT: call void @sideeffect0() |
| 117 | +; CHECK-NEXT: br i1 [[C:%.*]], label [[DISPATCH:%.*]], label [[END:%.*]] |
| 118 | +; CHECK: dispatch: |
| 119 | +; CHECK-NEXT: call void @sideeffect1() |
| 120 | +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]] |
| 121 | +; CHECK-NEXT: [[VAL:%.*]] = add i32 [[A]], [[B]] |
| 122 | +; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[CMP]], i32 [[VAL]], i32 0, !unpredictable !1 |
| 123 | +; CHECK-NEXT: br label [[END]] |
| 124 | +; CHECK: end: |
| 125 | +; CHECK-NEXT: [[RES:%.*]] = phi i32 [ -1, [[ENTRY:%.*]] ], [ [[SPEC_SELECT]], [[DISPATCH]] ] |
| 126 | +; CHECK-NEXT: call void @sideeffect2() |
| 127 | +; CHECK-NEXT: ret i32 [[RES]] |
| 128 | +; |
| 129 | +entry: |
| 130 | + call void @sideeffect0() |
| 131 | + br i1 %c, label %dispatch, label %end |
| 132 | + |
| 133 | +dispatch: |
| 134 | + call void @sideeffect1() |
| 135 | + %cmp = icmp eq i32 %a, %b |
| 136 | + br i1 %cmp, label %cond.true, label %end, !unpredictable !1 ; unpredictable |
| 137 | + |
| 138 | +cond.true: |
| 139 | + %val = add i32 %a, %b |
| 140 | + br label %end |
| 141 | + |
| 142 | +end: |
| 143 | + %res = phi i32 [ -1, %entry ], [ 0, %dispatch ], [ %val, %cond.true ] |
| 144 | + call void @sideeffect2() |
| 145 | + ret i32 %res |
| 146 | +} |
| 147 | + |
| 148 | +define i32 @unpredictable_yet_taken(i1 %c, i32 %a, i32 %b) { |
| 149 | +; CHECK-LABEL: @unpredictable_yet_taken( |
| 150 | +; CHECK-NEXT: entry: |
| 151 | +; CHECK-NEXT: call void @sideeffect0() |
| 152 | +; CHECK-NEXT: br i1 [[C:%.*]], label [[DISPATCH:%.*]], label [[END:%.*]] |
| 153 | +; CHECK: dispatch: |
| 154 | +; CHECK-NEXT: call void @sideeffect1() |
| 155 | +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]] |
| 156 | +; CHECK-NEXT: [[VAL:%.*]] = add i32 [[A]], [[B]] |
| 157 | +; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[CMP]], i32 [[VAL]], i32 0, !prof [[PROF0]], !unpredictable !1 |
| 158 | +; CHECK-NEXT: br label [[END]] |
| 159 | +; CHECK: end: |
| 160 | +; CHECK-NEXT: [[RES:%.*]] = phi i32 [ -1, [[ENTRY:%.*]] ], [ [[SPEC_SELECT]], [[DISPATCH]] ] |
| 161 | +; CHECK-NEXT: call void @sideeffect2() |
| 162 | +; CHECK-NEXT: ret i32 [[RES]] |
| 163 | +; |
| 164 | +entry: |
| 165 | + call void @sideeffect0() |
| 166 | + br i1 %c, label %dispatch, label %end |
| 167 | + |
| 168 | +dispatch: |
| 169 | + call void @sideeffect1() |
| 170 | + %cmp = icmp eq i32 %a, %b |
| 171 | + br i1 %cmp, label %cond.true, label %end, !prof !0, !unpredictable !1 ; likely branches to %cond.true, yet unpredictable |
| 172 | + |
| 173 | +cond.true: |
| 174 | + %val = add i32 %a, %b |
| 175 | + br label %end |
| 176 | + |
| 177 | +end: |
| 178 | + %res = phi i32 [ -1, %entry ], [ 0, %dispatch ], [ %val, %cond.true ] |
| 179 | + call void @sideeffect2() |
| 180 | + ret i32 %res |
| 181 | +} |
| 182 | + |
| 183 | +define i32 @unpredictable_yet_nontaken(i1 %c, i32 %a, i32 %b) { |
| 184 | +; CHECK-LABEL: @unpredictable_yet_nontaken( |
| 185 | +; CHECK-NEXT: entry: |
| 186 | +; CHECK-NEXT: call void @sideeffect0() |
| 187 | +; CHECK-NEXT: br i1 [[C:%.*]], label [[DISPATCH:%.*]], label [[END:%.*]] |
| 188 | +; CHECK: dispatch: |
| 189 | +; CHECK-NEXT: call void @sideeffect1() |
| 190 | +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]] |
| 191 | +; CHECK-NEXT: [[VAL:%.*]] = add i32 [[A]], [[B]] |
| 192 | +; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[CMP]], i32 0, i32 [[VAL]], !prof [[PROF0]], !unpredictable !1 |
| 193 | +; CHECK-NEXT: br label [[END]] |
| 194 | +; CHECK: end: |
| 195 | +; CHECK-NEXT: [[RES:%.*]] = phi i32 [ -1, [[ENTRY:%.*]] ], [ [[SPEC_SELECT]], [[DISPATCH]] ] |
| 196 | +; CHECK-NEXT: call void @sideeffect2() |
| 197 | +; CHECK-NEXT: ret i32 [[RES]] |
| 198 | +; |
| 199 | +entry: |
| 200 | + call void @sideeffect0() |
| 201 | + br i1 %c, label %dispatch, label %end |
| 202 | + |
| 203 | +dispatch: |
| 204 | + call void @sideeffect1() |
| 205 | + %cmp = icmp eq i32 %a, %b |
| 206 | + br i1 %cmp, label %end, label %cond.true, !prof !0, !unpredictable !1 ; likely branches to %end, yet unpredictable |
| 207 | + |
| 208 | +cond.true: |
| 209 | + %val = add i32 %a, %b |
| 210 | + br label %end |
| 211 | + |
| 212 | +end: |
| 213 | + %res = phi i32 [ -1, %entry ], [ 0, %dispatch ], [ %val, %cond.true ] |
| 214 | + call void @sideeffect2() |
| 215 | + ret i32 %res |
| 216 | +} |
| 217 | + |
| 218 | +!0 = !{!"branch_weights", i32 99, i32 1} |
| 219 | +!1 = !{} |
| 220 | + |
| 221 | +; CHECK: !0 = !{!"branch_weights", i32 99, i32 1} |
| 222 | +; CHECK: !1 = !{} |
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