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[clang] Define SwiftInfo for RISCVTargetCodeGenInfo (llvm#82152)
For Embedded Swift, let's unblock building for RISC-V boards (e.g. ESP32-C6). This isn't trying to add full RISC-V support to Swift / Embedded Swift, it's just fixing the immediate blocker (not having SwiftInfo defined blocks all compilations).
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clang/lib/CodeGen/Targets/RISCV.cpp

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@@ -529,7 +529,10 @@ class RISCVTargetCodeGenInfo : public TargetCodeGenInfo {
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RISCVTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, unsigned XLen,
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unsigned FLen, bool EABI)
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: TargetCodeGenInfo(
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std::make_unique<RISCVABIInfo>(CGT, XLen, FLen, EABI)) {}
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std::make_unique<RISCVABIInfo>(CGT, XLen, FLen, EABI)) {
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SwiftInfo =
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std::make_unique<SwiftABIInfo>(CGT, /*SwiftErrorInRegister=*/false);
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}
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void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
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CodeGen::CodeGenModule &CGM) const override {

clang/test/CodeGenCXX/arm-swiftcall.cpp

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@@ -1,5 +1,9 @@
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// RUN: %clang_cc1 -triple armv7-apple-darwin9 -emit-llvm -o - %s -Wno-return-type-c-linkage -std=c++03 | FileCheck %s -check-prefixes=CHECK
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// For now just check that the RISC-V triples are accepted, but don't check the IR, as swiftcall is not yet supported.
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// RUN: %clang_cc1 -triple riscv32-unknown-linux-gnu -emit-llvm -o - %s -Wno-return-type-c-linkage -std=c++03
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// RUN: %clang_cc1 -triple riscv64-unknown-linux-gnu -emit-llvm -o - %s -Wno-return-type-c-linkage -std=c++03
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// This isn't really testing anything ARM-specific; it's just a convenient
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// 32-bit platform.
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