We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
2 parents 42b9a69 + 84e3c6f commit b8b8c88Copy full SHA for b8b8c88
llvm/lib/Target/RISCV/RISCVVMV0Elimination.cpp
@@ -88,12 +88,12 @@ bool RISCVVMV0Elimination::runOnMachineFunction(MachineFunction &MF) {
88
return false;
89
90
MachineRegisterInfo &MRI = MF.getRegInfo();
91
- const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
92
const TargetInstrInfo *TII = ST->getInstrInfo();
93
94
#ifndef NDEBUG
95
// Assert that we won't clobber any existing reads of v0 where we need to
96
// insert copies.
+ const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
97
ReversePostOrderTraversal<MachineBasicBlock *> RPOT(&*MF.begin());
98
for (MachineBasicBlock *MBB : RPOT) {
99
bool V0Clobbered = false;
0 commit comments