[RISCV] Add scheduling model for SiFive P800 processors (llvm#139316)

The scheduling model for SiFive P800 series cores. They have 6 integer
pipes, 2 floating point pipes, and 2 vector pipes.

https://chipsandcheese.com/p/hot-chips-2023-sifives-p870-takes-risc-v-further

The tests are meant to have the same coverage as its P600 counterpart.

Author: mshockwave

llvm/lib/Target/RISCV/RISCV.td

@@ -58,6 +58,7 @@ include "RISCVSchedSiFive7.td"
 include "RISCVSchedSiFiveP400.td"
 include "RISCVSchedSiFiveP500.td"
 include "RISCVSchedSiFiveP600.td"
+include "RISCVSchedSiFiveP800.td"
 include "RISCVSchedSpacemitX60.td"
 include "RISCVSchedSyntacoreSCR1.td"
 include "RISCVSchedSyntacoreSCR345.td"

llvm/lib/Target/RISCV/RISCVProcessors.td

@@ -365,7 +365,7 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model,
                                        TuneVXRMPipelineFlush,
                                        TunePostRAScheduler]>;
 
-def SIFIVE_P870 : RISCVProcessorModel<"sifive-p870", NoSchedModel,
+def SIFIVE_P870 : RISCVProcessorModel<"sifive-p870", SiFiveP800Model,
                                       !listconcat(RVA23U64Features,
                                       [FeatureStdExtZama16b,
                                        FeatureStdExtZfh,