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Merge commit '0bb9a27c9895' from llvm.org/master into apple/master
2 parents 02105de + 0bb9a27 commit b97c841

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4 files changed

+464
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‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 48 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -288,15 +288,27 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
288288
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
289289
setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
290290
setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
291+
setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
292+
setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i64, Custom);
293+
setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i128, Custom);
291294
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
292295
setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
293296
setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
297+
setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
298+
setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i64, Custom);
299+
setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i128, Custom);
294300
setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
295301
setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
296302
setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
303+
setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Custom);
304+
setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i64, Custom);
305+
setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i128, Custom);
297306
setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
298307
setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
299308
setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
309+
setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Custom);
310+
setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Custom);
311+
setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i128, Custom);
300312
setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
301313
setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
302314
setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Custom);
@@ -2332,9 +2344,16 @@ getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
23322344

23332345
SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
23342346
RTLIB::Libcall Call) const {
2335-
SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
2347+
bool IsStrict = Op->isStrictFPOpcode();
2348+
unsigned Offset = IsStrict ? 1 : 0;
2349+
SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
2350+
SmallVector<SDValue, 2> Ops(Op->op_begin() + Offset, Op->op_end());
23362351
MakeLibCallOptions CallOptions;
2337-
return makeLibCall(DAG, Call, MVT::f128, Ops, CallOptions, SDLoc(Op)).first;
2352+
SDValue Result;
2353+
SDLoc dl(Op);
2354+
std::tie(Result, Chain) = makeLibCall(DAG, Call, Op.getValueType(), Ops,
2355+
CallOptions, dl, Chain);
2356+
return IsStrict ? DAG.getMergeValues({Result, Chain}, dl) : Result;
23382357
}
23392358

23402359
// Returns true if the given Op is the overflow flag result of an overflow
@@ -2595,32 +2614,34 @@ SDValue AArch64TargetLowering::LowerVectorFP_TO_INT(SDValue Op,
25952614

25962615
SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
25972616
SelectionDAG &DAG) const {
2598-
if (Op.getOperand(0).getValueType().isVector())
2617+
bool IsStrict = Op->isStrictFPOpcode();
2618+
SDValue SrcVal = Op.getOperand(IsStrict ? 1 : 0);
2619+
2620+
if (SrcVal.getValueType().isVector())
25992621
return LowerVectorFP_TO_INT(Op, DAG);
26002622

26012623
// f16 conversions are promoted to f32 when full fp16 is not supported.
2602-
if (Op.getOperand(0).getValueType() == MVT::f16 &&
2603-
!Subtarget->hasFullFP16()) {
2624+
if (SrcVal.getValueType() == MVT::f16 && !Subtarget->hasFullFP16()) {
2625+
assert(!IsStrict && "Lowering of strict fp16 not yet implemented");
26042626
SDLoc dl(Op);
26052627
return DAG.getNode(
26062628
Op.getOpcode(), dl, Op.getValueType(),
2607-
DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, Op.getOperand(0)));
2629+
DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, SrcVal));
26082630
}
26092631

2610-
if (Op.getOperand(0).getValueType() != MVT::f128) {
2632+
if (SrcVal.getValueType() != MVT::f128) {
26112633
// It's legal except when f128 is involved
26122634
return Op;
26132635
}
26142636

26152637
RTLIB::Libcall LC;
2616-
if (Op.getOpcode() == ISD::FP_TO_SINT)
2617-
LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
2638+
if (Op.getOpcode() == ISD::FP_TO_SINT ||
2639+
Op.getOpcode() == ISD::STRICT_FP_TO_SINT)
2640+
LC = RTLIB::getFPTOSINT(SrcVal.getValueType(), Op.getValueType());
26182641
else
2619-
LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
2642+
LC = RTLIB::getFPTOUINT(SrcVal.getValueType(), Op.getValueType());
26202643

2621-
SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
2622-
MakeLibCallOptions CallOptions;
2623-
return makeLibCall(DAG, LC, Op.getValueType(), Ops, CallOptions, SDLoc(Op)).first;
2644+
return LowerF128Call(Op, DAG, LC);
26242645
}
26252646

26262647
static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
@@ -2656,18 +2677,22 @@ SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
26562677
if (Op.getValueType().isVector())
26572678
return LowerVectorINT_TO_FP(Op, DAG);
26582679

2680+
bool IsStrict = Op->isStrictFPOpcode();
2681+
SDValue SrcVal = Op.getOperand(IsStrict ? 1 : 0);
2682+
26592683
// f16 conversions are promoted to f32 when full fp16 is not supported.
26602684
if (Op.getValueType() == MVT::f16 &&
26612685
!Subtarget->hasFullFP16()) {
2686+
assert(!IsStrict && "Lowering of strict fp16 not yet implemented");
26622687
SDLoc dl(Op);
26632688
return DAG.getNode(
26642689
ISD::FP_ROUND, dl, MVT::f16,
2665-
DAG.getNode(Op.getOpcode(), dl, MVT::f32, Op.getOperand(0)),
2690+
DAG.getNode(Op.getOpcode(), dl, MVT::f32, SrcVal),
26662691
DAG.getIntPtrConstant(0, dl));
26672692
}
26682693

26692694
// i128 conversions are libcalls.
2670-
if (Op.getOperand(0).getValueType() == MVT::i128)
2695+
if (SrcVal.getValueType() == MVT::i128)
26712696
return SDValue();
26722697

26732698
// Other conversions are legal, unless it's to the completely software-based
@@ -2676,10 +2701,11 @@ SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
26762701
return Op;
26772702

26782703
RTLIB::Libcall LC;
2679-
if (Op.getOpcode() == ISD::SINT_TO_FP)
2680-
LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
2704+
if (Op.getOpcode() == ISD::SINT_TO_FP ||
2705+
Op.getOpcode() == ISD::STRICT_SINT_TO_FP)
2706+
LC = RTLIB::getSINTTOFP(SrcVal.getValueType(), Op.getValueType());
26812707
else
2682-
LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
2708+
LC = RTLIB::getUINTTOFP(SrcVal.getValueType(), Op.getValueType());
26832709

26842710
return LowerF128Call(Op, DAG, LC);
26852711
}
@@ -3272,9 +3298,13 @@ SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
32723298
return LowerPREFETCH(Op, DAG);
32733299
case ISD::SINT_TO_FP:
32743300
case ISD::UINT_TO_FP:
3301+
case ISD::STRICT_SINT_TO_FP:
3302+
case ISD::STRICT_UINT_TO_FP:
32753303
return LowerINT_TO_FP(Op, DAG);
32763304
case ISD::FP_TO_SINT:
32773305
case ISD::FP_TO_UINT:
3306+
case ISD::STRICT_FP_TO_SINT:
3307+
case ISD::STRICT_FP_TO_UINT:
32783308
return LowerFP_TO_INT(Op, DAG);
32793309
case ISD::FSINCOS:
32803310
return LowerFSINCOS(Op, DAG);

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -3429,10 +3429,10 @@ defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns
34293429
defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>;
34303430
defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_aarch64_neon_fcvtps>;
34313431
defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>;
3432-
defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
3433-
defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
3434-
defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
3435-
defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
3432+
defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", any_fp_to_sint>;
3433+
defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>;
3434+
defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", any_fp_to_sint>;
3435+
defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>;
34363436

34373437
multiclass FPToIntegerIntPats<Intrinsic round, string INST> {
34383438
def : Pat<(i32 (round f16:$Rn)), (!cast<Instruction>(INST # UWHr) $Rn)>;
@@ -3504,8 +3504,8 @@ def : Pat<(i64 (llround f64:$Rn)),
35043504
// Scaled integer to floating point conversion instructions.
35053505
//===----------------------------------------------------------------------===//
35063506

3507-
defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
3508-
defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
3507+
defm SCVTF : IntegerToFP<0, "scvtf", any_sint_to_fp>;
3508+
defm UCVTF : IntegerToFP<1, "ucvtf", any_uint_to_fp>;
35093509

35103510
//===----------------------------------------------------------------------===//
35113511
// Unscaled integer to floating point conversion instruction.

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