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Thomas Preud'homme
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Improve STRICT_FSETCC codegen in absence of no NaN
As for SETCC, use a less expensive condition code when generating STRICT_FSETCC if the node is known not to have Nan. Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D91972
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‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7126,7 +7126,10 @@ void SelectionDAGBuilder::visitConstrainedFPIntrinsic(
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case ISD::STRICT_FSETCC:
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case ISD::STRICT_FSETCCS: {
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auto *FPCmp = dyn_cast<ConstrainedFPCmpIntrinsic>(&FPI);
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Opers.push_back(DAG.getCondCode(getFCmpCondCode(FPCmp->getPredicate())));
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ISD::CondCode Condition = getFCmpCondCode(FPCmp->getPredicate());
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if (TM.Options.NoNaNsFPMath)
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Condition = getFCmpCodeWithoutNaN(Condition);
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Opers.push_back(DAG.getCondCode(Condition));
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break;
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}
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}

‎llvm/test/CodeGen/AArch64/arm64-constrained-fcmp-no-nans-opt.ll

Lines changed: 112 additions & 0 deletions
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@@ -0,0 +1,112 @@
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; RUN: llc < %s -mtriple=arm64-eabi -mattr=+fullfp16 -enable-no-nans-fp-math | FileCheck %s
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declare i1 @llvm.experimental.constrained.fcmp.f32(float, float, metadata, metadata)
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declare i1 @llvm.experimental.constrained.fcmp.f64(double, double, metadata, metadata)
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; CHECK-LABEL: @f32_constrained_fcmp_ueq
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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define i1 @f32_constrained_fcmp_ueq(float %a, float %b) nounwind ssp {
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%cmp = tail call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ueq", metadata !"fpexcept.strict")
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ret i1 %cmp
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}
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; CHECK-LABEL: @f32_constrained_fcmp_une
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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define i1 @f32_constrained_fcmp_une(float %a, float %b) nounwind ssp {
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%cmp = tail call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"une", metadata !"fpexcept.strict")
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ret i1 %cmp
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}
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; CHECK-LABEL: @f32_constrained_fcmp_ugt
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset w0, gt
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; CHECK-NEXT: ret
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define i1 @f32_constrained_fcmp_ugt(float %a, float %b) nounwind ssp {
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%cmp = tail call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ugt", metadata !"fpexcept.strict")
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ret i1 %cmp
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}
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; CHECK-LABEL: @f32_constrained_fcmp_uge
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset w0, ge
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; CHECK-NEXT: ret
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define i1 @f32_constrained_fcmp_uge(float %a, float %b) nounwind ssp {
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%cmp = tail call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"uge", metadata !"fpexcept.strict")
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ret i1 %cmp
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}
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; CHECK-LABEL: @f32_constrained_fcmp_ult
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset w0, lt
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; CHECK-NEXT: ret
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define i1 @f32_constrained_fcmp_ult(float %a, float %b) nounwind ssp {
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%cmp = tail call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ult", metadata !"fpexcept.strict")
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ret i1 %cmp
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}
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; CHECK-LABEL: @f32_constrained_fcmp_ule
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset w0, le
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; CHECK-NEXT: ret
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define i1 @f32_constrained_fcmp_ule(float %a, float %b) nounwind ssp {
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%cmp = tail call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ule", metadata !"fpexcept.strict")
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ret i1 %cmp
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}
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; CHECK-LABEL: @f64_constrained_fcmp_ueq
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; CHECK: fcmp d0, d1
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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define i1 @f64_constrained_fcmp_ueq(double %a, double %b) nounwind ssp {
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%cmp = tail call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"ueq", metadata !"fpexcept.strict")
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ret i1 %cmp
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}
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; CHECK-LABEL: @f64_constrained_fcmp_une
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; CHECK: fcmp d0, d1
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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define i1 @f64_constrained_fcmp_une(double %a, double %b) nounwind ssp {
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%cmp = tail call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"une", metadata !"fpexcept.strict")
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ret i1 %cmp
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}
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; CHECK-LABEL: @f64_constrained_fcmp_ugt
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; CHECK: fcmp d0, d1
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; CHECK-NEXT: cset w0, gt
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; CHECK-NEXT: ret
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define i1 @f64_constrained_fcmp_ugt(double %a, double %b) nounwind ssp {
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%cmp = tail call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"ugt", metadata !"fpexcept.strict")
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ret i1 %cmp
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}
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; CHECK-LABEL: @f64_constrained_fcmp_uge
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; CHECK: fcmp d0, d1
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; CHECK-NEXT: cset w0, ge
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; CHECK-NEXT: ret
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define i1 @f64_constrained_fcmp_uge(double %a, double %b) nounwind ssp {
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%cmp = tail call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"uge", metadata !"fpexcept.strict")
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ret i1 %cmp
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}
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; CHECK-LABEL: @f64_constrained_fcmp_ult
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; CHECK: fcmp d0, d1
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; CHECK-NEXT: cset w0, lt
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; CHECK-NEXT: ret
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define i1 @f64_constrained_fcmp_ult(double %a, double %b) nounwind ssp {
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%cmp = tail call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"ult", metadata !"fpexcept.strict")
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ret i1 %cmp
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}
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; CHECK-LABEL: @f64_constrained_fcmp_ule
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; CHECK: fcmp d0, d1
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; CHECK-NEXT: cset w0, le
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; CHECK-NEXT: ret
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define i1 @f64_constrained_fcmp_ule(double %a, double %b) nounwind ssp {
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%cmp = tail call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"ule", metadata !"fpexcept.strict")
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ret i1 %cmp
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}

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