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1 parent f88ce07 commit be15284Copy full SHA for be15284
mlir/test/Conversion/StandardToSPIRV/std-ops-to-spirv.mlir
@@ -181,7 +181,6 @@ module attributes {
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max_compute_workgroup_size = dense<[128, 128, 64]> : vector<3xi32>}>
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} {
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-// CHECK-LEBEL: @int_vector4_invalid
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func @int_vector4_invalid(%arg0: vector<4xi64>) {
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// expected-error @+2 {{bitwidth emulation is not implemented yet on unsigned op}}
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// expected-error @+1 {{op requires the same type for all operands and results}}
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