Skip to content

Commit be15dfa

Browse files
arichardsonarichardson
committed
[NFC] Use EVT instead of bool for getSetCCInverse()
Summary: The use of a boolean isInteger flag (generally initialized using VT.isInteger()) caused errors in our out-of-tree CHERI backend (https://github.com/CTSRD-CHERI/llvm-project). In our backend, pointers use a separate ValueType (iFATPTR) and therefore .isInteger() returns false. This meant that getSetCCInverse() was using the floating-point variant and generated incorrect code for us: `(void *)0x12033091e < (void *)0xffffffffffffffff` would return false. Committing this change will significantly reduce our merge conflicts for each upstream merge. Reviewers: spatel, bogner Reviewed By: bogner Subscribers: wuzish, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, jrtc27, atanasyan, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70917
1 parent 2bbd32f commit be15dfa

File tree

13 files changed

+68
-59
lines changed

13 files changed

+68
-59
lines changed

‎llvm/include/llvm/CodeGen/ISDOpcodes.h

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,8 @@
1313
#ifndef LLVM_CODEGEN_ISDOPCODES_H
1414
#define LLVM_CODEGEN_ISDOPCODES_H
1515

16+
#include "llvm/CodeGen/ValueTypes.h"
17+
1618
namespace llvm {
1719

1820
/// ISD namespace - This namespace contains an enum which represents all of the
@@ -1082,7 +1084,7 @@ namespace ISD {
10821084

10831085
/// Return the operation corresponding to !(X op Y), where 'op' is a valid
10841086
/// SetCC operation.
1085-
CondCode getSetCCInverse(CondCode Operation, bool isInteger);
1087+
CondCode getSetCCInverse(CondCode Operation, EVT Type);
10861088

10871089
/// Return the operation corresponding to (Y op X) when given the operation
10881090
/// for (X op Y).
@@ -1091,12 +1093,12 @@ namespace ISD {
10911093
/// Return the result of a logical OR between different comparisons of
10921094
/// identical values: ((X op1 Y) | (X op2 Y)). This function returns
10931095
/// SETCC_INVALID if it is not possible to represent the resultant comparison.
1094-
CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger);
1096+
CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, EVT Type);
10951097

10961098
/// Return the result of a logical AND between different comparisons of
10971099
/// identical values: ((X op1 Y) & (X op2 Y)). This function returns
10981100
/// SETCC_INVALID if it is not possible to represent the resultant comparison.
1099-
CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
1101+
CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, EVT Type);
11001102

11011103
} // end llvm::ISD namespace
11021104

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4641,8 +4641,8 @@ SDValue DAGCombiner::foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1,
46414641
// (and (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC)
46424642
// (or (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC)
46434643
if (LL == RL && LR == RR) {
4644-
ISD::CondCode NewCC = IsAnd ? ISD::getSetCCAndOperation(CC0, CC1, IsInteger)
4645-
: ISD::getSetCCOrOperation(CC0, CC1, IsInteger);
4644+
ISD::CondCode NewCC = IsAnd ? ISD::getSetCCAndOperation(CC0, CC1, OpVT)
4645+
: ISD::getSetCCOrOperation(CC0, CC1, OpVT);
46464646
if (NewCC != ISD::SETCC_INVALID &&
46474647
(!LegalOperations ||
46484648
(TLI.isCondCodeLegal(NewCC, LL.getSimpleValueType()) &&
@@ -7047,7 +7047,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
70477047
SDValue LHS, RHS, CC;
70487048
if (TLI.isConstTrueVal(N1.getNode()) && isSetCCEquivalent(N0, LHS, RHS, CC)) {
70497049
ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
7050-
LHS.getValueType().isInteger());
7050+
LHS.getValueType());
70517051
if (!LegalOperations ||
70527052
TLI.isCondCodeLegal(NotCC, LHS.getSimpleValueType())) {
70537053
switch (N0Opcode) {
@@ -20348,7 +20348,7 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
2034820348
(!LegalOperations || TLI.isOperationLegal(ISD::SETCC, CmpOpVT))) {
2034920349

2035020350
if (Swap) {
20351-
CC = ISD::getSetCCInverse(CC, CmpOpVT.isInteger());
20351+
CC = ISD::getSetCCInverse(CC, CmpOpVT);
2035220352
std::swap(N2C, N3C);
2035320353
}
2035420354

‎llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1659,7 +1659,7 @@ bool SelectionDAGLegalize::LegalizeSetCCCondCode(
16591659
}
16601660
// Swapping operands didn't work. Try inverting the condition.
16611661
bool NeedSwap = false;
1662-
InvCC = getSetCCInverse(CCCode, OpVT.isInteger());
1662+
InvCC = getSetCCInverse(CCCode, OpVT);
16631663
if (!TLI.isCondCodeLegalOrCustom(InvCC, OpVT)) {
16641664
// If inverting the condition is not enough, try swapping operands
16651665
// on top of it.
@@ -3614,8 +3614,7 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
36143614
// Try to legalize by inverting the condition. This is for targets that
36153615
// might support an ordered version of a condition, but not the unordered
36163616
// version (or vice versa).
3617-
ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp,
3618-
Tmp1.getValueType().isInteger());
3617+
ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp, Tmp1.getValueType());
36193618
if (TLI.isCondCodeLegalOrCustom(InvCC, Tmp1.getSimpleValueType())) {
36203619
// Use the new condition code and swap true and false
36213620
Legalized = true;

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -356,9 +356,10 @@ ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) {
356356
(OldG << 2)); // New L bit.
357357
}
358358

359-
ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) {
359+
ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, EVT Type) {
360+
bool IsInteger = Type.isInteger();
360361
unsigned Operation = Op;
361-
if (isInteger)
362+
if (IsInteger)
362363
Operation ^= 7; // Flip L, G, E bits, but not U.
363364
else
364365
Operation ^= 15; // Flip all of the condition bits.
@@ -389,7 +390,8 @@ static int isSignedOp(ISD::CondCode Opcode) {
389390
}
390391

391392
ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2,
392-
bool IsInteger) {
393+
EVT Type) {
394+
bool IsInteger = Type.isInteger();
393395
if (IsInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3)
394396
// Cannot fold a signed integer setcc with an unsigned integer setcc.
395397
return ISD::SETCC_INVALID;
@@ -409,7 +411,8 @@ ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2,
409411
}
410412

411413
ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2,
412-
bool IsInteger) {
414+
EVT Type) {
415+
bool IsInteger = Type.isInteger();
413416
if (IsInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3)
414417
// Cannot fold a signed setcc with an unsigned setcc.
415418
return ISD::SETCC_INVALID;

‎llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Lines changed: 12 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -390,8 +390,10 @@ void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
390390
NewRHS = DAG.getConstant(0, dl, RetVT);
391391

392392
CCCode = getCmpLibcallCC(LC1);
393-
if (ShouldInvertCC)
394-
CCCode = getSetCCInverse(CCCode, /*isInteger=*/true);
393+
if (ShouldInvertCC) {
394+
assert(RetVT.isInteger());
395+
CCCode = getSetCCInverse(CCCode, RetVT);
396+
}
395397

396398
if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
397399
SDValue Tmp = DAG.getNode(
@@ -2812,7 +2814,8 @@ SDValue TargetLowering::foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
28122814
// Note that where Y is variable and is known to have at most one bit set
28132815
// (for example, if it is Z & 1) we cannot do this; the expressions are not
28142816
// equivalent when Y == 0.
2815-
Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2817+
assert(OpVT.isInteger());
2818+
Cond = ISD::getSetCCInverse(Cond, OpVT);
28162819
if (DCI.isBeforeLegalizeOps() ||
28172820
isCondCodeLegal(Cond, N0.getSimpleValueType()))
28182821
return DAG.getSetCC(DL, VT, N0, Zero, Cond);
@@ -2901,7 +2904,8 @@ SDValue TargetLowering::optimizeSetCCOfSignedTruncationCheck(
29012904
// What if we invert constants? (and the target predicate)
29022905
I1.negate();
29032906
I01.negate();
2904-
NewCond = getSetCCInverse(NewCond, /*isInteger=*/true);
2907+
assert(XVT.isInteger());
2908+
NewCond = getSetCCInverse(NewCond, XVT);
29052909
if (!checkConstants())
29062910
return SDValue();
29072911
// Great, e.g. got icmp uge i16 (add i16 %x, -128), -256
@@ -3137,7 +3141,8 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
31373141
// (ctpop x) != 1 --> (x == 0) || ((x & x-1) != 0)
31383142
SDValue Zero = DAG.getConstant(0, dl, CTVT);
31393143
SDValue NegOne = DAG.getAllOnesConstant(dl, CTVT);
3140-
ISD::CondCode InvCond = ISD::getSetCCInverse(Cond, true);
3144+
assert(CTVT.isInteger());
3145+
ISD::CondCode InvCond = ISD::getSetCCInverse(Cond, CTVT);
31413146
SDValue Add = DAG.getNode(ISD::ADD, dl, CTVT, CTOp, NegOne);
31423147
SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Add);
31433148
SDValue LHS = DAG.getSetCC(dl, VT, CTOp, Zero, InvCond);
@@ -3228,7 +3233,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
32283233

32293234
ISD::CondCode InvCond = ISD::getSetCCInverse(
32303235
cast<CondCodeSDNode>(TopSetCC.getOperand(2))->get(),
3231-
TopSetCC.getOperand(0).getValueType().isInteger());
3236+
TopSetCC.getOperand(0).getValueType());
32323237
return DAG.getSetCC(dl, VT, TopSetCC.getOperand(0),
32333238
TopSetCC.getOperand(1),
32343239
InvCond);
@@ -3392,8 +3397,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
33923397
return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
33933398
// Invert the condition.
33943399
ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
3395-
CC = ISD::getSetCCInverse(CC,
3396-
N0.getOperand(0).getValueType().isInteger());
3400+
CC = ISD::getSetCCInverse(CC, N0.getOperand(0).getValueType());
33973401
if (DCI.isBeforeLegalizeOps() ||
33983402
isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType()))
33993403
return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 17 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1614,7 +1614,8 @@ static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
16141614
// All of the compare-mask comparisons are ordered, but we can switch
16151615
// between the two by a double inversion. E.g. ULE == !OGT.
16161616
Invert = true;
1617-
changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
1617+
changeFPCCToAArch64CC(getSetCCInverse(CC, /* FP inverse */ MVT::f32),
1618+
CondCode, CondCode2);
16181619
break;
16191620
}
16201621
}
@@ -1861,7 +1862,7 @@ static SDValue emitConjunctionRec(SelectionDAG &DAG, SDValue Val,
18611862
ISD::CondCode CC = cast<CondCodeSDNode>(Val->getOperand(2))->get();
18621863
bool isInteger = LHS.getValueType().isInteger();
18631864
if (Negate)
1864-
CC = getSetCCInverse(CC, isInteger);
1865+
CC = getSetCCInverse(CC, LHS.getValueType());
18651866
SDLoc DL(Val);
18661867
// Determine OutCC and handle FP special case.
18671868
if (isInteger) {
@@ -2333,7 +2334,7 @@ static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
23332334
if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
23342335
std::swap(TVal, FVal);
23352336
std::swap(CTVal, CFVal);
2336-
CC = ISD::getSetCCInverse(CC, true);
2337+
CC = ISD::getSetCCInverse(CC, LHS.getValueType());
23372338
}
23382339

23392340
// If the constants line up, perform the transform!
@@ -5026,8 +5027,8 @@ SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
50265027

50275028
if (LHS.getValueType().isInteger()) {
50285029
SDValue CCVal;
5029-
SDValue Cmp =
5030-
getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
5030+
SDValue Cmp = getAArch64Cmp(
5031+
LHS, RHS, ISD::getSetCCInverse(CC, LHS.getValueType()), CCVal, DAG, dl);
50315032

50325033
// Note that we inverted the condition above, so we reverse the order of
50335034
// the true and false operands here. This will allow the setcc to be
@@ -5046,7 +5047,8 @@ SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
50465047
AArch64CC::CondCode CC1, CC2;
50475048
changeFPCCToAArch64CC(CC, CC1, CC2);
50485049
if (CC2 == AArch64CC::AL) {
5049-
changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
5050+
changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, LHS.getValueType()), CC1,
5051+
CC2);
50505052
SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
50515053

50525054
// Note that we inverted the condition above, so we reverse the order of
@@ -5107,26 +5109,26 @@ SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
51075109
if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
51085110
std::swap(TVal, FVal);
51095111
std::swap(CTVal, CFVal);
5110-
CC = ISD::getSetCCInverse(CC, true);
5112+
CC = ISD::getSetCCInverse(CC, LHS.getValueType());
51115113
} else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
51125114
std::swap(TVal, FVal);
51135115
std::swap(CTVal, CFVal);
5114-
CC = ISD::getSetCCInverse(CC, true);
5116+
CC = ISD::getSetCCInverse(CC, LHS.getValueType());
51155117
} else if (TVal.getOpcode() == ISD::XOR) {
51165118
// If TVal is a NOT we want to swap TVal and FVal so that we can match
51175119
// with a CSINV rather than a CSEL.
51185120
if (isAllOnesConstant(TVal.getOperand(1))) {
51195121
std::swap(TVal, FVal);
51205122
std::swap(CTVal, CFVal);
5121-
CC = ISD::getSetCCInverse(CC, true);
5123+
CC = ISD::getSetCCInverse(CC, LHS.getValueType());
51225124
}
51235125
} else if (TVal.getOpcode() == ISD::SUB) {
51245126
// If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
51255127
// that we can match with a CSNEG rather than a CSEL.
51265128
if (isNullConstant(TVal.getOperand(0))) {
51275129
std::swap(TVal, FVal);
51285130
std::swap(CTVal, CFVal);
5129-
CC = ISD::getSetCCInverse(CC, true);
5131+
CC = ISD::getSetCCInverse(CC, LHS.getValueType());
51305132
}
51315133
} else if (CTVal && CFVal) {
51325134
const int64_t TrueVal = CTVal->getSExtValue();
@@ -5169,7 +5171,7 @@ SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
51695171
if (Swap) {
51705172
std::swap(TVal, FVal);
51715173
std::swap(CTVal, CFVal);
5172-
CC = ISD::getSetCCInverse(CC, true);
5174+
CC = ISD::getSetCCInverse(CC, LHS.getValueType());
51735175
}
51745176

51755177
if (Opcode != AArch64ISD::CSEL) {
@@ -10430,10 +10432,10 @@ static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
1043010432
MVT::i32);
1043110433
Cmp = *InfoAndKind.Info.AArch64.Cmp;
1043210434
} else
10433-
Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
10434-
*InfoAndKind.Info.Generic.Opnd1,
10435-
ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
10436-
CCVal, DAG, dl);
10435+
Cmp = getAArch64Cmp(
10436+
*InfoAndKind.Info.Generic.Opnd0, *InfoAndKind.Info.Generic.Opnd1,
10437+
ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, CmpVT), CCVal, DAG,
10438+
dl);
1043710439

1043810440
EVT VT = Op->getValueType(0);
1043910441
LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, dl, VT));

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3568,8 +3568,8 @@ SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,
35683568
// select (setcc x, y), k, x -> select (setccinv x, y), x, k
35693569

35703570
SDLoc SL(N);
3571-
ISD::CondCode NewCC = getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3572-
LHS.getValueType().isInteger());
3571+
ISD::CondCode NewCC =
3572+
getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), LHS.getValueType());
35733573

35743574
SDValue NewCond = DAG.getSetCC(SL, Cond.getValueType(), LHS, RHS, NewCC);
35753575
return DAG.getNode(ISD::SELECT, SL, VT, NewCond, False, True);

‎llvm/lib/Target/AMDGPU/R600ISelLowering.cpp

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -974,8 +974,7 @@ SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
974974
// Move hardware True/False values to the correct operand.
975975
if (isHWTrueValue(False) && isHWFalseValue(True)) {
976976
ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
977-
ISD::CondCode InverseCC =
978-
ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
977+
ISD::CondCode InverseCC = ISD::getSetCCInverse(CCOpcode, CompareVT);
979978
if (isCondCodeLegal(InverseCC, CompareVT.getSimpleVT())) {
980979
std::swap(False, True);
981980
CC = DAG.getCondCode(InverseCC);
@@ -1015,7 +1014,7 @@ SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
10151014
CC = DAG.getCondCode(CCSwapped);
10161015
} else {
10171016
// Try inverting the conditon and then swapping the operands
1018-
ISD::CondCode CCInv = ISD::getSetCCInverse(CCOpcode, CompareVT.isInteger());
1017+
ISD::CondCode CCInv = ISD::getSetCCInverse(CCOpcode, CompareVT);
10191018
CCSwapped = ISD::getSetCCSwappedOperands(CCInv);
10201019
if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) {
10211020
std::swap(True, False);
@@ -1041,7 +1040,7 @@ SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
10411040
case ISD::SETONE:
10421041
case ISD::SETUNE:
10431042
case ISD::SETNE:
1044-
CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
1043+
CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT);
10451044
Temp = True;
10461045
True = False;
10471046
False = Temp;
@@ -1993,8 +1992,7 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
19931992
case ISD::SETNE: return LHS;
19941993
case ISD::SETEQ: {
19951994
ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get();
1996-
LHSCC = ISD::getSetCCInverse(LHSCC,
1997-
LHS.getOperand(0).getValueType().isInteger());
1995+
LHSCC = ISD::getSetCCInverse(LHSCC, LHS.getOperand(0).getValueType());
19981996
if (DCI.isBeforeLegalizeOps() ||
19991997
isCondCodeLegal(LHSCC, LHS.getOperand(0).getSimpleValueType()))
20001998
return DAG.getSelectCC(DL,

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -4952,7 +4952,7 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
49524952
Opcode = ARMISD::CSINC;
49534953
std::swap(TrueVal, FalseVal);
49544954
std::swap(TVal, FVal);
4955-
CC = ISD::getSetCCInverse(CC, true);
4955+
CC = ISD::getSetCCInverse(CC, LHS.getValueType());
49564956
}
49574957

49584958
if (Opcode) {
@@ -4962,7 +4962,7 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
49624962
HasLowerConstantMaterializationCost(FVal, TVal, Subtarget)) {
49634963
std::swap(TrueVal, FalseVal);
49644964
std::swap(TVal, FVal);
4965-
CC = ISD::getSetCCInverse(CC, true);
4965+
CC = ISD::getSetCCInverse(CC, LHS.getValueType());
49664966
}
49674967

49684968
// Attempt to use ZR checking TVal is 0, possibly inverting the condition
@@ -4971,7 +4971,7 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
49714971
if (FVal == 0 && Opcode != ARMISD::CSINC) {
49724972
std::swap(TrueVal, FalseVal);
49734973
std::swap(TVal, FVal);
4974-
CC = ISD::getSetCCInverse(CC, true);
4974+
CC = ISD::getSetCCInverse(CC, LHS.getValueType());
49754975
}
49764976
if (TVal == 0)
49774977
TrueVal = DAG.getRegister(ARM::ZR, MVT::i32);
@@ -5015,7 +5015,7 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
50155015
ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
50165016
if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
50175017
CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
5018-
CC = ISD::getSetCCInverse(CC, true);
5018+
CC = ISD::getSetCCInverse(CC, LHS.getValueType());
50195019
std::swap(TrueVal, FalseVal);
50205020
}
50215021
}
@@ -14226,7 +14226,7 @@ static SDValue PerformHWLoopCombine(SDNode *N,
1422614226
return SDValue();
1422714227

1422814228
if (Negate)
14229-
CC = ISD::getSetCCInverse(CC, true);
14229+
CC = ISD::getSetCCInverse(CC, /* Integer inverse */ MVT::i32);
1423014230

1423114231
auto IsTrueIfZero = [](ISD::CondCode CC, int Imm) {
1423214232
return (CC == ISD::SETEQ && Imm == 0) ||

‎llvm/lib/Target/Mips/MipsISelLowering.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -709,7 +709,8 @@ static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
709709
SDValue True = N->getOperand(1);
710710

711711
SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
712-
SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
712+
SetCC.getOperand(1),
713+
ISD::getSetCCInverse(CC, SetCC.getValueType()));
713714

714715
return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
715716
}
@@ -743,7 +744,8 @@ static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
743744
if (Diff == -1) {
744745
ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
745746
SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
746-
SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
747+
SetCC.getOperand(1),
748+
ISD::getSetCCInverse(CC, SetCC.getValueType()));
747749
return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
748750
}
749751

0 commit comments

Comments
 (0)