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[RISCV] Add tests for deinterleave(2-8) shuffles
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‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=riscv32 -mattr=+v \
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; RUN: -lower-interleaved-accesses=false -verify-machineinstrs \
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; RUN: | FileCheck %s --check-prefixes=CHECK,RV32V
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; RUN: llc < %s -mtriple=riscv64 -mattr=+v \
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; RUN: -lower-interleaved-accesses=false -verify-machineinstrs \
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; RUN: | FileCheck %s --check-prefixes=CHECK,RV64V
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define void @deinterleave3_0_i8(ptr %in, ptr %out) {
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; CHECK-LABEL: deinterleave3_0_i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vid.v v9
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; CHECK-NEXT: li a0, 3
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; CHECK-NEXT: vmul.vx v9, v9, a0
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; CHECK-NEXT: vrgather.vv v10, v8, v9
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; CHECK-NEXT: vadd.vi v9, v9, -8
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; CHECK-NEXT: li a0, 56
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; CHECK-NEXT: vmv.s.x v0, a0
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; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
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; CHECK-NEXT: vslidedown.vi v8, v8, 8
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
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; CHECK-NEXT: vrgather.vv v10, v8, v9, v0.t
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; CHECK-NEXT: vse8.v v10, (a1)
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; CHECK-NEXT: ret
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entry:
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%0 = load <16 x i8>, ptr %in, align 1
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%shuffle.i5 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 undef, i32 undef>
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store <8 x i8> %shuffle.i5, ptr %out, align 1
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ret void
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}
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define void @deinterleave3_8_i8(ptr %in, ptr %out) {
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; CHECK-LABEL: deinterleave3_8_i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vmv.v.i v9, 1
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; CHECK-NEXT: vid.v v10
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; CHECK-NEXT: li a0, 3
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; CHECK-NEXT: vmadd.vx v10, a0, v9
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; CHECK-NEXT: vrgather.vv v9, v8, v10
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; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
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; CHECK-NEXT: vslidedown.vi v8, v8, 8
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; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; CHECK-NEXT: vsrl.vi v10, v8, 8
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; CHECK-NEXT: vsll.vi v8, v8, 8
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; CHECK-NEXT: li a0, 24
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; CHECK-NEXT: vmv.s.x v0, a0
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; CHECK-NEXT: vor.vv v8, v8, v10
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
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; CHECK-NEXT: vse8.v v8, (a1)
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; CHECK-NEXT: ret
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entry:
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%0 = load <16 x i8>, ptr %in, align 1
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%shuffle.i5 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 undef, i32 undef, i32 undef>
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store <8 x i8> %shuffle.i5, ptr %out, align 1
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ret void
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}
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define void @deinterleave4_0_i8(ptr %in, ptr %out) {
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; CHECK-LABEL: deinterleave4_0_i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
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; CHECK-NEXT: vslidedown.vi v9, v8, 4
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vwaddu.vv v10, v8, v9
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; CHECK-NEXT: li a0, -1
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; CHECK-NEXT: vwmaccu.vx v10, a0, v9
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; CHECK-NEXT: vmv.v.i v0, 12
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vid.v v9
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; CHECK-NEXT: vsll.vi v9, v9, 2
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; CHECK-NEXT: vadd.vi v9, v9, -8
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; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
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; CHECK-NEXT: vslidedown.vi v8, v8, 8
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
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; CHECK-NEXT: vrgather.vv v10, v8, v9, v0.t
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; CHECK-NEXT: vse8.v v10, (a1)
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; CHECK-NEXT: ret
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entry:
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%0 = load <16 x i8>, ptr %in, align 1
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%shuffle.i5 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 undef, i32 undef, i32 undef, i32 undef>
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store <8 x i8> %shuffle.i5, ptr %out, align 1
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ret void
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}
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define void @deinterleave4_8_i8(ptr %in, ptr %out) {
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; CHECK-LABEL: deinterleave4_8_i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vmv.v.i v9, -9
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; CHECK-NEXT: vid.v v10
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; CHECK-NEXT: li a0, 5
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; CHECK-NEXT: vmacc.vx v9, a0, v10
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; CHECK-NEXT: vsll.vi v10, v10, 2
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; CHECK-NEXT: vadd.vi v10, v10, 1
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; CHECK-NEXT: vrgather.vv v11, v8, v10
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; CHECK-NEXT: vmv.v.i v0, 12
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; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
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; CHECK-NEXT: vslidedown.vi v8, v8, 8
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
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; CHECK-NEXT: vrgather.vv v11, v8, v9, v0.t
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; CHECK-NEXT: vse8.v v11, (a1)
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; CHECK-NEXT: ret
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entry:
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%0 = load <16 x i8>, ptr %in, align 1
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%shuffle.i5 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 1, i32 5, i32 9, i32 14, i32 undef, i32 undef, i32 undef, i32 undef>
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store <8 x i8> %shuffle.i5, ptr %out, align 1
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ret void
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}
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define void @deinterleave5_0_i8(ptr %in, ptr %out) {
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; CHECK-LABEL: deinterleave5_0_i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vid.v v9
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; CHECK-NEXT: li a0, 5
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; CHECK-NEXT: vmul.vx v9, v9, a0
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; CHECK-NEXT: vrgather.vv v10, v8, v9
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; CHECK-NEXT: vadd.vi v9, v9, -8
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; CHECK-NEXT: vmv.v.i v0, 12
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; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
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; CHECK-NEXT: vslidedown.vi v8, v8, 8
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
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; CHECK-NEXT: vrgather.vv v10, v8, v9, v0.t
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; CHECK-NEXT: vse8.v v10, (a1)
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; CHECK-NEXT: ret
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entry:
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%0 = load <16 x i8>, ptr %in, align 1
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%shuffle.i5 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 0, i32 5, i32 10, i32 15, i32 undef, i32 undef, i32 undef, i32 undef>
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store <8 x i8> %shuffle.i5, ptr %out, align 1
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ret void
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}
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define void @deinterleave5_8_i8(ptr %in, ptr %out) {
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; CHECK-LABEL: deinterleave5_8_i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vmv.v.i v9, 1
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; CHECK-NEXT: vid.v v10
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; CHECK-NEXT: li a0, 5
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; CHECK-NEXT: vmadd.vx v10, a0, v9
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; CHECK-NEXT: vrgather.vv v9, v8, v10
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; CHECK-NEXT: vmv.v.i v0, 4
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; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
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; CHECK-NEXT: vslidedown.vi v8, v8, 8
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
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; CHECK-NEXT: vrgather.vi v9, v8, 3, v0.t
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; CHECK-NEXT: vse8.v v9, (a1)
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; CHECK-NEXT: ret
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entry:
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%0 = load <16 x i8>, ptr %in, align 1
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%shuffle.i5 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 1, i32 6, i32 11, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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store <8 x i8> %shuffle.i5, ptr %out, align 1
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ret void
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}
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define void @deinterleave6_0_i8(ptr %in, ptr %out) {
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; CHECK-LABEL: deinterleave6_0_i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vid.v v9
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; CHECK-NEXT: li a0, 6
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; CHECK-NEXT: vmul.vx v9, v9, a0
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; CHECK-NEXT: vrgather.vv v10, v8, v9
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; CHECK-NEXT: vmv.v.i v0, 4
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; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
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; CHECK-NEXT: vslidedown.vi v8, v8, 8
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
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; CHECK-NEXT: vrgather.vi v10, v8, 4, v0.t
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; CHECK-NEXT: vse8.v v10, (a1)
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; CHECK-NEXT: ret
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entry:
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%0 = load <16 x i8>, ptr %in, align 1
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%shuffle.i5 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 0, i32 6, i32 12, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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store <8 x i8> %shuffle.i5, ptr %out, align 1
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ret void
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}
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define void @deinterleave6_8_i8(ptr %in, ptr %out) {
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; CHECK-LABEL: deinterleave6_8_i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vmv.v.i v9, 1
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; CHECK-NEXT: vid.v v10
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; CHECK-NEXT: li a0, 6
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; CHECK-NEXT: vmadd.vx v10, a0, v9
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; CHECK-NEXT: vrgather.vv v9, v8, v10
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; CHECK-NEXT: vmv.v.i v0, 4
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; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
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; CHECK-NEXT: vslidedown.vi v8, v8, 8
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
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; CHECK-NEXT: vrgather.vi v9, v8, 5, v0.t
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; CHECK-NEXT: vse8.v v9, (a1)
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; CHECK-NEXT: ret
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entry:
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%0 = load <16 x i8>, ptr %in, align 1
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%shuffle.i5 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 1, i32 7, i32 13, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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store <8 x i8> %shuffle.i5, ptr %out, align 1
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ret void
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}
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define void @deinterleave7_0_i8(ptr %in, ptr %out) {
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; CHECK-LABEL: deinterleave7_0_i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vid.v v9
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; CHECK-NEXT: li a0, 7
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; CHECK-NEXT: vmul.vx v9, v9, a0
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; CHECK-NEXT: vrgather.vv v10, v8, v9
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; CHECK-NEXT: vmv.v.i v0, 4
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; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
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; CHECK-NEXT: vslidedown.vi v8, v8, 8
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
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; CHECK-NEXT: vrgather.vi v10, v8, 6, v0.t
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; CHECK-NEXT: vse8.v v10, (a1)
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; CHECK-NEXT: ret
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entry:
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%0 = load <16 x i8>, ptr %in, align 1
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%shuffle.i5 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 0, i32 7, i32 14, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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store <8 x i8> %shuffle.i5, ptr %out, align 1
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ret void
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}
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define void @deinterleave7_8_i8(ptr %in, ptr %out) {
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; CHECK-LABEL: deinterleave7_8_i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vmv.v.i v9, -6
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; CHECK-NEXT: vid.v v10
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; CHECK-NEXT: li a0, 6
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; CHECK-NEXT: vmadd.vx v10, a0, v9
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; CHECK-NEXT: vmv.v.i v0, 6
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; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
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; CHECK-NEXT: vslidedown.vi v9, v8, 8
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
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; CHECK-NEXT: vrgather.vi v11, v8, 1
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; CHECK-NEXT: vrgather.vv v11, v9, v10, v0.t
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; CHECK-NEXT: vse8.v v11, (a1)
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; CHECK-NEXT: ret
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entry:
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%0 = load <16 x i8>, ptr %in, align 1
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%shuffle.i5 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 1, i32 8, i32 14, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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store <8 x i8> %shuffle.i5, ptr %out, align 1
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ret void
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}
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define void @deinterleave8_0_i8(ptr %in, ptr %out) {
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; CHECK-LABEL: deinterleave8_0_i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
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; CHECK-NEXT: vslidedown.vi v9, v8, 8
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; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
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; CHECK-NEXT: vslideup.vi v8, v9, 1
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vse8.v v8, (a1)
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; CHECK-NEXT: ret
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entry:
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%0 = load <16 x i8>, ptr %in, align 1
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%shuffle.i5 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 0, i32 8, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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store <8 x i8> %shuffle.i5, ptr %out, align 1
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ret void
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}
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define void @deinterleave8_8_i8(ptr %in, ptr %out) {
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; CHECK-LABEL: deinterleave8_8_i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vmv.v.i v0, -3
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; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
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; CHECK-NEXT: vslidedown.vi v9, v8, 8
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
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; CHECK-NEXT: vrgather.vi v9, v8, 1, v0.t
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; CHECK-NEXT: vse8.v v9, (a1)
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; CHECK-NEXT: ret
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entry:
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%0 = load <16 x i8>, ptr %in, align 1
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%shuffle.i5 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 1, i32 9, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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store <8 x i8> %shuffle.i5, ptr %out, align 1
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ret void
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}
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; RV32V: {{.*}}
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; RV64V: {{.*}}

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