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[AArch64][GlobalISel] Add support for selection of vector G_SHL with immediates.
Only implemented for the type combinations already supported for G_SHL. Differential Revision: https://reviews.llvm.org/D71153
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-21
lines changed

3 files changed

+267
-21
lines changed

‎llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp

Lines changed: 71 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1006,6 +1006,64 @@ bool AArch64InstructionSelector::selectCompareBranch(
10061006
return true;
10071007
}
10081008

1009+
/// Returns the element immediate value of a vector shift operand if found.
1010+
/// This needs to detect a splat-like operation, e.g. a G_BUILD_VECTOR.
1011+
static Optional<int64_t> getVectorShiftImm(Register Reg,
1012+
MachineRegisterInfo &MRI) {
1013+
const LLT Ty = MRI.getType(Reg);
1014+
assert(Ty.isVector() && "Expected a *vector* shift operand");
1015+
MachineInstr *OpMI = MRI.getVRegDef(Reg);
1016+
assert(OpMI && "Expected to find a vreg def for vector shift operand");
1017+
if (OpMI->getOpcode() != TargetOpcode::G_BUILD_VECTOR)
1018+
return None;
1019+
1020+
// Check all operands are identical immediates.
1021+
int64_t ImmVal = 0;
1022+
for (unsigned Idx = 1; Idx < OpMI->getNumOperands(); ++Idx) {
1023+
auto VRegAndVal = getConstantVRegValWithLookThrough(OpMI->getOperand(Idx).getReg(), MRI);
1024+
if (!VRegAndVal)
1025+
return None;
1026+
1027+
if (Idx == 1)
1028+
ImmVal = VRegAndVal->Value;
1029+
if (ImmVal != VRegAndVal->Value)
1030+
return None;
1031+
}
1032+
1033+
return ImmVal;
1034+
}
1035+
1036+
/// Matches and returns the shift immediate value for a SHL instruction given
1037+
/// a shift operand.
1038+
static Optional<int64_t> getVectorSHLImm(LLT SrcTy, Register Reg, MachineRegisterInfo &MRI) {
1039+
Optional<int64_t> ShiftImm = getVectorShiftImm(Reg, MRI);
1040+
if (!ShiftImm)
1041+
return None;
1042+
// Check the immediate is in range for a SHL.
1043+
int64_t Imm = *ShiftImm;
1044+
if (Imm < 0)
1045+
return None;
1046+
switch (SrcTy.getElementType().getSizeInBits()) {
1047+
case 8:
1048+
if (Imm > 7)
1049+
return None;
1050+
break;
1051+
case 16:
1052+
if (Imm > 15)
1053+
return None;
1054+
break;
1055+
case 32:
1056+
if (Imm > 31)
1057+
return None;
1058+
break;
1059+
case 64:
1060+
if (Imm > 63)
1061+
return None;
1062+
break;
1063+
}
1064+
return Imm;
1065+
}
1066+
10091067
bool AArch64InstructionSelector::selectVectorSHL(
10101068
MachineInstr &I, MachineRegisterInfo &MRI) const {
10111069
assert(I.getOpcode() == TargetOpcode::G_SHL);
@@ -1017,21 +1075,29 @@ bool AArch64InstructionSelector::selectVectorSHL(
10171075
if (!Ty.isVector())
10181076
return false;
10191077

1078+
// Check if we have a vector of constants on RHS that we can select as the
1079+
// immediate form.
1080+
Optional<int64_t> ImmVal = getVectorSHLImm(Ty, Src2Reg, MRI);
1081+
10201082
unsigned Opc = 0;
10211083
if (Ty == LLT::vector(2, 64)) {
1022-
Opc = AArch64::USHLv2i64;
1084+
Opc = ImmVal ? AArch64::SHLv2i64_shift : AArch64::USHLv2i64;
10231085
} else if (Ty == LLT::vector(4, 32)) {
1024-
Opc = AArch64::USHLv4i32;
1086+
Opc = ImmVal ? AArch64::SHLv4i32_shift : AArch64::USHLv4i32;
10251087
} else if (Ty == LLT::vector(2, 32)) {
1026-
Opc = AArch64::USHLv2i32;
1088+
Opc = ImmVal ? AArch64::SHLv2i32_shift : AArch64::USHLv2i32;
10271089
} else {
10281090
LLVM_DEBUG(dbgs() << "Unhandled G_SHL type");
10291091
return false;
10301092
}
10311093

10321094
MachineIRBuilder MIB(I);
1033-
auto UShl = MIB.buildInstr(Opc, {DstReg}, {Src1Reg, Src2Reg});
1034-
constrainSelectedInstRegOperands(*UShl, TII, TRI, RBI);
1095+
auto Shl = MIB.buildInstr(Opc, {DstReg}, {Src1Reg});
1096+
if (ImmVal)
1097+
Shl.addImm(*ImmVal);
1098+
else
1099+
Shl.addUse(Src2Reg);
1100+
constrainSelectedInstRegOperands(*Shl, TII, TRI, RBI);
10351101
I.eraseFromParent();
10361102
return true;
10371103
}

‎llvm/test/CodeGen/AArch64/GlobalISel/select-vector-icmp.mir

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -2293,17 +2293,17 @@ body: |
22932293
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[MOVi32imm]], %subreg.ssub
22942294
; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[MOVi32imm]]
22952295
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
2296-
; CHECK: [[USHLv2i32_:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY]], [[COPY2]]
2296+
; CHECK: [[SHLv2i32_shift:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY]], 16
22972297
; CHECK: [[NEGv2i32_:%[0-9]+]]:fpr64 = NEGv2i32 [[COPY2]]
2298-
; CHECK: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[USHLv2i32_]], [[NEGv2i32_]]
2298+
; CHECK: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift]], [[NEGv2i32_]]
22992299
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 16
23002300
; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
23012301
; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[MOVi32imm1]], %subreg.ssub
23022302
; CHECK: [[INSvi32gpr1:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG1]], 1, [[MOVi32imm1]]
23032303
; CHECK: [[COPY3:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr1]].dsub
2304-
; CHECK: [[USHLv2i32_1:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY1]], [[COPY3]]
2304+
; CHECK: [[SHLv2i32_shift1:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY1]], 16
23052305
; CHECK: [[NEGv2i32_1:%[0-9]+]]:fpr64 = NEGv2i32 [[COPY3]]
2306-
; CHECK: [[SSHLv2i32_1:%[0-9]+]]:fpr64 = SSHLv2i32 [[USHLv2i32_1]], [[NEGv2i32_1]]
2306+
; CHECK: [[SSHLv2i32_1:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift1]], [[NEGv2i32_1]]
23072307
; CHECK: [[CMGTv2i32_:%[0-9]+]]:fpr64 = CMGTv2i32 [[SSHLv2i32_]], [[SSHLv2i32_1]]
23082308
; CHECK: $d0 = COPY [[CMGTv2i32_]]
23092309
; CHECK: RET_ReallyLR implicit $d0
@@ -2591,17 +2591,17 @@ body: |
25912591
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[MOVi32imm]], %subreg.ssub
25922592
; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[MOVi32imm]]
25932593
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
2594-
; CHECK: [[USHLv2i32_:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY]], [[COPY2]]
2594+
; CHECK: [[SHLv2i32_shift:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY]], 16
25952595
; CHECK: [[NEGv2i32_:%[0-9]+]]:fpr64 = NEGv2i32 [[COPY2]]
2596-
; CHECK: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[USHLv2i32_]], [[NEGv2i32_]]
2596+
; CHECK: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift]], [[NEGv2i32_]]
25972597
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 16
25982598
; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
25992599
; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[MOVi32imm1]], %subreg.ssub
26002600
; CHECK: [[INSvi32gpr1:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG1]], 1, [[MOVi32imm1]]
26012601
; CHECK: [[COPY3:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr1]].dsub
2602-
; CHECK: [[USHLv2i32_1:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY1]], [[COPY3]]
2602+
; CHECK: [[SHLv2i32_shift1:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY1]], 16
26032603
; CHECK: [[NEGv2i32_1:%[0-9]+]]:fpr64 = NEGv2i32 [[COPY3]]
2604-
; CHECK: [[SSHLv2i32_1:%[0-9]+]]:fpr64 = SSHLv2i32 [[USHLv2i32_1]], [[NEGv2i32_1]]
2604+
; CHECK: [[SSHLv2i32_1:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift1]], [[NEGv2i32_1]]
26052605
; CHECK: [[CMGEv2i32_:%[0-9]+]]:fpr64 = CMGEv2i32 [[SSHLv2i32_]], [[SSHLv2i32_1]]
26062606
; CHECK: $d0 = COPY [[CMGEv2i32_]]
26072607
; CHECK: RET_ReallyLR implicit $d0
@@ -2889,17 +2889,17 @@ body: |
28892889
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[MOVi32imm]], %subreg.ssub
28902890
; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[MOVi32imm]]
28912891
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
2892-
; CHECK: [[USHLv2i32_:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY]], [[COPY2]]
2892+
; CHECK: [[SHLv2i32_shift:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY]], 16
28932893
; CHECK: [[NEGv2i32_:%[0-9]+]]:fpr64 = NEGv2i32 [[COPY2]]
2894-
; CHECK: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[USHLv2i32_]], [[NEGv2i32_]]
2894+
; CHECK: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift]], [[NEGv2i32_]]
28952895
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 16
28962896
; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
28972897
; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[MOVi32imm1]], %subreg.ssub
28982898
; CHECK: [[INSvi32gpr1:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG1]], 1, [[MOVi32imm1]]
28992899
; CHECK: [[COPY3:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr1]].dsub
2900-
; CHECK: [[USHLv2i32_1:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY1]], [[COPY3]]
2900+
; CHECK: [[SHLv2i32_shift1:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY1]], 16
29012901
; CHECK: [[NEGv2i32_1:%[0-9]+]]:fpr64 = NEGv2i32 [[COPY3]]
2902-
; CHECK: [[SSHLv2i32_1:%[0-9]+]]:fpr64 = SSHLv2i32 [[USHLv2i32_1]], [[NEGv2i32_1]]
2902+
; CHECK: [[SSHLv2i32_1:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift1]], [[NEGv2i32_1]]
29032903
; CHECK: [[CMGTv2i32_:%[0-9]+]]:fpr64 = CMGTv2i32 [[SSHLv2i32_1]], [[SSHLv2i32_]]
29042904
; CHECK: $d0 = COPY [[CMGTv2i32_]]
29052905
; CHECK: RET_ReallyLR implicit $d0
@@ -3187,17 +3187,17 @@ body: |
31873187
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[MOVi32imm]], %subreg.ssub
31883188
; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[MOVi32imm]]
31893189
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
3190-
; CHECK: [[USHLv2i32_:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY]], [[COPY2]]
3190+
; CHECK: [[SHLv2i32_shift:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY]], 16
31913191
; CHECK: [[NEGv2i32_:%[0-9]+]]:fpr64 = NEGv2i32 [[COPY2]]
3192-
; CHECK: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[USHLv2i32_]], [[NEGv2i32_]]
3192+
; CHECK: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift]], [[NEGv2i32_]]
31933193
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 16
31943194
; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
31953195
; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[MOVi32imm1]], %subreg.ssub
31963196
; CHECK: [[INSvi32gpr1:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG1]], 1, [[MOVi32imm1]]
31973197
; CHECK: [[COPY3:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr1]].dsub
3198-
; CHECK: [[USHLv2i32_1:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY1]], [[COPY3]]
3198+
; CHECK: [[SHLv2i32_shift1:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY1]], 16
31993199
; CHECK: [[NEGv2i32_1:%[0-9]+]]:fpr64 = NEGv2i32 [[COPY3]]
3200-
; CHECK: [[SSHLv2i32_1:%[0-9]+]]:fpr64 = SSHLv2i32 [[USHLv2i32_1]], [[NEGv2i32_1]]
3200+
; CHECK: [[SSHLv2i32_1:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift1]], [[NEGv2i32_1]]
32013201
; CHECK: [[CMGEv2i32_:%[0-9]+]]:fpr64 = CMGEv2i32 [[SSHLv2i32_1]], [[SSHLv2i32_]]
32023202
; CHECK: $d0 = COPY [[CMGEv2i32_]]
32033203
; CHECK: RET_ReallyLR implicit $d0

‎llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir

Lines changed: 180 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,79 @@ body: |
2828
$d0 = COPY %2(<2 x s32>)
2929
RET_ReallyLR implicit $d0
3030
31+
...
32+
---
33+
name: shl_v2i32_imm
34+
alignment: 4
35+
legalized: true
36+
regBankSelected: true
37+
tracksRegLiveness: true
38+
registers:
39+
- { id: 0, class: fpr }
40+
- { id: 1, class: fpr }
41+
- { id: 2, class: gpr }
42+
- { id: 3, class: fpr }
43+
liveins:
44+
- { reg: '$d0' }
45+
frameInfo:
46+
maxAlignment: 1
47+
machineFunctionInfo: {}
48+
body: |
49+
bb.1:
50+
liveins: $d0
51+
52+
; CHECK-LABEL: name: shl_v2i32_imm
53+
; CHECK: liveins: $d0
54+
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
55+
; CHECK: [[SHLv2i32_shift:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY]], 24
56+
; CHECK: $d0 = COPY [[SHLv2i32_shift]]
57+
; CHECK: RET_ReallyLR implicit $d0
58+
%0:fpr(<2 x s32>) = COPY $d0
59+
%2:gpr(s32) = G_CONSTANT i32 24
60+
%1:fpr(<2 x s32>) = G_BUILD_VECTOR %2(s32), %2(s32)
61+
%3:fpr(<2 x s32>) = G_SHL %0, %1(<2 x s32>)
62+
$d0 = COPY %3(<2 x s32>)
63+
RET_ReallyLR implicit $d0
64+
65+
...
66+
---
67+
name: shl_v2i32_imm_out_of_range
68+
alignment: 4
69+
legalized: true
70+
regBankSelected: true
71+
tracksRegLiveness: true
72+
registers:
73+
- { id: 0, class: fpr }
74+
- { id: 1, class: fpr }
75+
- { id: 2, class: gpr }
76+
- { id: 3, class: fpr }
77+
liveins:
78+
- { reg: '$d0' }
79+
frameInfo:
80+
maxAlignment: 1
81+
machineFunctionInfo: {}
82+
body: |
83+
bb.1:
84+
liveins: $d0
85+
86+
; CHECK-LABEL: name: shl_v2i32_imm_out_of_range
87+
; CHECK: liveins: $d0
88+
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
89+
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 40
90+
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
91+
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[MOVi32imm]], %subreg.ssub
92+
; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[MOVi32imm]]
93+
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
94+
; CHECK: [[USHLv2i32_:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY]], [[COPY1]]
95+
; CHECK: $d0 = COPY [[USHLv2i32_]]
96+
; CHECK: RET_ReallyLR implicit $d0
97+
%0:fpr(<2 x s32>) = COPY $d0
98+
%2:gpr(s32) = G_CONSTANT i32 40
99+
%1:fpr(<2 x s32>) = G_BUILD_VECTOR %2(s32), %2(s32)
100+
%3:fpr(<2 x s32>) = G_SHL %0, %1(<2 x s32>)
101+
$d0 = COPY %3(<2 x s32>)
102+
RET_ReallyLR implicit $d0
103+
31104
...
32105
---
33106
name: shl_v4i32
@@ -57,6 +130,40 @@ body: |
57130
$q0 = COPY %2(<4 x s32>)
58131
RET_ReallyLR implicit $q0
59132
133+
...
134+
---
135+
name: shl_v4i32_imm
136+
alignment: 4
137+
legalized: true
138+
regBankSelected: true
139+
tracksRegLiveness: true
140+
registers:
141+
- { id: 0, class: fpr }
142+
- { id: 1, class: fpr }
143+
- { id: 2, class: gpr }
144+
- { id: 3, class: fpr }
145+
liveins:
146+
- { reg: '$q0' }
147+
frameInfo:
148+
maxAlignment: 1
149+
machineFunctionInfo: {}
150+
body: |
151+
bb.1:
152+
liveins: $q0
153+
154+
; CHECK-LABEL: name: shl_v4i32_imm
155+
; CHECK: liveins: $q0
156+
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
157+
; CHECK: [[SHLv4i32_shift:%[0-9]+]]:fpr128 = SHLv4i32_shift [[COPY]], 24
158+
; CHECK: $q0 = COPY [[SHLv4i32_shift]]
159+
; CHECK: RET_ReallyLR implicit $q0
160+
%0:fpr(<4 x s32>) = COPY $q0
161+
%2:gpr(s32) = G_CONSTANT i32 24
162+
%1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %2(s32), %2(s32), %2(s32)
163+
%3:fpr(<4 x s32>) = G_SHL %0, %1(<4 x s32>)
164+
$q0 = COPY %3(<4 x s32>)
165+
RET_ReallyLR implicit $q0
166+
60167
...
61168
---
62169
name: shl_v2i64
@@ -86,6 +193,79 @@ body: |
86193
$q0 = COPY %2(<2 x s64>)
87194
RET_ReallyLR implicit $q0
88195
196+
...
197+
---
198+
name: shl_v2i64_imm
199+
alignment: 4
200+
legalized: true
201+
regBankSelected: true
202+
tracksRegLiveness: true
203+
registers:
204+
- { id: 0, class: fpr }
205+
- { id: 1, class: fpr }
206+
- { id: 2, class: gpr }
207+
- { id: 3, class: fpr }
208+
liveins:
209+
- { reg: '$q0' }
210+
frameInfo:
211+
maxAlignment: 1
212+
machineFunctionInfo: {}
213+
body: |
214+
bb.1:
215+
liveins: $q0
216+
217+
; CHECK-LABEL: name: shl_v2i64_imm
218+
; CHECK: liveins: $q0
219+
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
220+
; CHECK: [[SHLv2i64_shift:%[0-9]+]]:fpr128 = SHLv2i64_shift [[COPY]], 24
221+
; CHECK: $q0 = COPY [[SHLv2i64_shift]]
222+
; CHECK: RET_ReallyLR implicit $q0
223+
%0:fpr(<2 x s64>) = COPY $q0
224+
%2:gpr(s64) = G_CONSTANT i64 24
225+
%1:fpr(<2 x s64>) = G_BUILD_VECTOR %2(s64), %2(s64)
226+
%3:fpr(<2 x s64>) = G_SHL %0, %1(<2 x s64>)
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$q0 = COPY %3(<2 x s64>)
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RET_ReallyLR implicit $q0
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...
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---
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name: shl_v2i64_imm_out_of_range
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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- { id: 2, class: gpr }
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- { id: 3, class: fpr }
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liveins:
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- { reg: '$q0' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.1:
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liveins: $q0
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; CHECK-LABEL: name: shl_v2i64_imm_out_of_range
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 70
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[SUBREG_TO_REG]], %subreg.dsub
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; CHECK: [[INSvi64gpr:%[0-9]+]]:fpr128 = INSvi64gpr [[INSERT_SUBREG]], 1, [[SUBREG_TO_REG]]
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; CHECK: [[USHLv2i64_:%[0-9]+]]:fpr128 = USHLv2i64 [[COPY]], [[INSvi64gpr]]
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; CHECK: $q0 = COPY [[USHLv2i64_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<2 x s64>) = COPY $q0
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%2:gpr(s64) = G_CONSTANT i64 70
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%1:fpr(<2 x s64>) = G_BUILD_VECTOR %2(s64), %2(s64)
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%3:fpr(<2 x s64>) = G_SHL %0, %1(<2 x s64>)
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$q0 = COPY %3(<2 x s64>)
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RET_ReallyLR implicit $q0
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89269
...
90270
---
91271
name: ashr_v2i32

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