Skip to content

Commit c7a0b26

Browse files
topperctopperc
committed
[X86][MC][Target] Initial backend support a tune CPU to support -mtune
This patch implements initial backend support for a -mtune CPU controlled by a "tune-cpu" function attribute. If the attribute is not present X86 will use the resolved CPU from target-cpu attribute or command line. This patch adds MC layer support a tune CPU. Each CPU now has two sets of features stored in their GenSubtargetInfo.inc tables . These features lists are passed separately to the Processor and ProcessorModel classes in tablegen. The tune list defaults to an empty list to avoid changes to non-X86. This annoyingly increases the size of static tables on all target as we now store 24 more bytes per CPU. I haven't quantified the overall impact, but I can if we're concerned. One new test is added to X86 to show a few tuning features with mismatched tune-cpu and target-cpu/target-feature attributes to demonstrate independent control. Another new test is added to demonstrate that the scheduler model follows the tune CPU. I have not added a -mtune to llc/opt or MC layer command line yet. With no attributes we'll just use the -mcpu for both. MC layer tools will always follow the normal CPU for tuning. Differential Revision: https://reviews.llvm.org/D85165
1 parent 0cceb54 commit c7a0b26

File tree

62 files changed

+211
-158
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

62 files changed

+211
-158
lines changed

‎llvm/include/llvm/CodeGen/TargetSubtargetInfo.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -58,8 +58,8 @@ class Triple;
5858
///
5959
class TargetSubtargetInfo : public MCSubtargetInfo {
6060
protected: // Can only create subclasses...
61-
TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
62-
ArrayRef<SubtargetFeatureKV> PF,
61+
TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU,
62+
StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
6363
ArrayRef<SubtargetSubTypeKV> PD,
6464
const MCWriteProcResEntry *WPR,
6565
const MCWriteLatencyEntry *WL,

‎llvm/include/llvm/MC/MCSubtargetInfo.h

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -54,6 +54,7 @@ struct SubtargetFeatureKV {
5454
struct SubtargetSubTypeKV {
5555
const char *Key; ///< K-V key string
5656
FeatureBitArray Implies; ///< K-V bit mask
57+
FeatureBitArray TuneImplies; ///< K-V bit mask
5758
const MCSchedModel *SchedModel;
5859

5960
/// Compare routine for std::lower_bound
@@ -74,6 +75,7 @@ struct SubtargetSubTypeKV {
7475
class MCSubtargetInfo {
7576
Triple TargetTriple;
7677
std::string CPU; // CPU being targeted.
78+
std::string TuneCPU; // CPU being tuned for.
7779
ArrayRef<SubtargetFeatureKV> ProcFeatures; // Processor feature list
7880
ArrayRef<SubtargetSubTypeKV> ProcDesc; // Processor descriptions
7981

@@ -90,8 +92,8 @@ class MCSubtargetInfo {
9092

9193
public:
9294
MCSubtargetInfo(const MCSubtargetInfo &) = default;
93-
MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
94-
ArrayRef<SubtargetFeatureKV> PF,
95+
MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU,
96+
StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
9597
ArrayRef<SubtargetSubTypeKV> PD,
9698
const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
9799
const MCReadAdvanceEntry *RA, const InstrStage *IS,
@@ -103,6 +105,7 @@ class MCSubtargetInfo {
103105

104106
const Triple &getTargetTriple() const { return TargetTriple; }
105107
StringRef getCPU() const { return CPU; }
108+
StringRef getTuneCPU() const { return TuneCPU; }
106109

107110
const FeatureBitset& getFeatureBits() const { return FeatureBits; }
108111
void setFeatureBits(const FeatureBitset &FeatureBits_) {
@@ -118,12 +121,12 @@ class MCSubtargetInfo {
118121
///
119122
/// FIXME: Find a way to stick this in the constructor, since it should only
120123
/// be called during initialization.
121-
void InitMCProcessorInfo(StringRef CPU, StringRef FS);
124+
void InitMCProcessorInfo(StringRef CPU, StringRef TuneCPU, StringRef FS);
122125

123126
public:
124-
/// Set the features to the default for the given CPU with an appended feature
125-
/// string.
126-
void setDefaultFeatures(StringRef CPU, StringRef FS);
127+
/// Set the features to the default for the given CPU and TuneCPU, with ano
128+
/// appended feature string.
129+
void setDefaultFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
127130

128131
/// Toggle a feature and return the re-computed feature bits.
129132
/// This version does not change the implied bits.

‎llvm/include/llvm/Target/Target.td

Lines changed: 11 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1558,7 +1558,8 @@ class ComplexDeprecationPredicate<string dep> {
15581558
// by the scheduler. Each Processor definition requires corresponding
15591559
// instruction itineraries.
15601560
//
1561-
class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
1561+
class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f,
1562+
list<SubtargetFeature> tunef = []> {
15621563
// Name - Chip set name. Used by command line (-mcpu=) to determine the
15631564
// appropriate target chip.
15641565
//
@@ -1574,6 +1575,12 @@ class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
15741575

15751576
// Features - list of
15761577
list<SubtargetFeature> Features = f;
1578+
1579+
// TuneFeatures - list of features for tuning for this CPU. If the target
1580+
// supports -mtune, this should contain the list of features used to make
1581+
// microarchitectural optimization decisions for a given processor. While
1582+
// Features should contain the architectural features for the processor.
1583+
list<SubtargetFeature> TuneFeatures = tunef;
15771584
}
15781585

15791586
// ProcessorModel allows subtargets to specify the more general
@@ -1582,8 +1589,9 @@ class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
15821589
//
15831590
// Although this class always passes NoItineraries to the Processor
15841591
// class, the SchedMachineModel may still define valid Itineraries.
1585-
class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f>
1586-
: Processor<n, NoItineraries, f> {
1592+
class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f,
1593+
list<SubtargetFeature> tunef = []>
1594+
: Processor<n, NoItineraries, f, tunef> {
15871595
let SchedModel = m;
15881596
}
15891597

‎llvm/lib/CodeGen/TargetSubtargetInfo.cpp

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -15,13 +15,12 @@
1515
using namespace llvm;
1616

1717
TargetSubtargetInfo::TargetSubtargetInfo(
18-
const Triple &TT, StringRef CPU, StringRef FS,
18+
const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS,
1919
ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetSubTypeKV> PD,
20-
const MCWriteProcResEntry *WPR,
21-
const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
22-
const InstrStage *IS, const unsigned *OC, const unsigned *FP)
23-
: MCSubtargetInfo(TT, CPU, FS, PF, PD, WPR, WL, RA, IS, OC, FP) {
24-
}
20+
const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
21+
const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC,
22+
const unsigned *FP)
23+
: MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD, WPR, WL, RA, IS, OC, FP) {}
2524

2625
TargetSubtargetInfo::~TargetSubtargetInfo() = default;
2726

‎llvm/lib/MC/MCSubtargetInfo.cpp

Lines changed: 29 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -147,7 +147,7 @@ static void cpuHelp(ArrayRef<SubtargetSubTypeKV> CPUTable) {
147147
PrintOnce = true;
148148
}
149149

150-
static FeatureBitset getFeatures(StringRef CPU, StringRef FS,
150+
static FeatureBitset getFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS,
151151
ArrayRef<SubtargetSubTypeKV> ProcDesc,
152152
ArrayRef<SubtargetFeatureKV> ProcFeatures) {
153153
SubtargetFeatures Features(FS);
@@ -178,6 +178,19 @@ static FeatureBitset getFeatures(StringRef CPU, StringRef FS,
178178
}
179179
}
180180

181+
if (!TuneCPU.empty()) {
182+
const SubtargetSubTypeKV *CPUEntry = Find(TuneCPU, ProcDesc);
183+
184+
// If there is a match
185+
if (CPUEntry) {
186+
// Set the features implied by this CPU feature, if any.
187+
SetImpliedBits(Bits, CPUEntry->TuneImplies.getAsBitset(), ProcFeatures);
188+
} else if (TuneCPU != CPU) {
189+
errs() << "'" << TuneCPU << "' is not a recognized processor for this "
190+
<< "target (ignoring processor)\n";
191+
}
192+
}
193+
181194
// Iterate through each feature
182195
for (const std::string &Feature : Features.getFeatures()) {
183196
// Check for help
@@ -192,30 +205,33 @@ static FeatureBitset getFeatures(StringRef CPU, StringRef FS,
192205
return Bits;
193206
}
194207

195-
void MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) {
196-
FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures);
197-
if (!CPU.empty())
198-
CPUSchedModel = &getSchedModelForCPU(CPU);
208+
void MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef TuneCPU,
209+
StringRef FS) {
210+
FeatureBits = getFeatures(CPU, TuneCPU, FS, ProcDesc, ProcFeatures);
211+
if (!TuneCPU.empty())
212+
CPUSchedModel = &getSchedModelForCPU(TuneCPU);
199213
else
200214
CPUSchedModel = &MCSchedModel::GetDefaultSchedModel();
201215
}
202216

203-
void MCSubtargetInfo::setDefaultFeatures(StringRef CPU, StringRef FS) {
204-
FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures);
217+
void MCSubtargetInfo::setDefaultFeatures(StringRef CPU, StringRef TuneCPU,
218+
StringRef FS) {
219+
FeatureBits = getFeatures(CPU, TuneCPU, FS, ProcDesc, ProcFeatures);
205220
}
206221

207-
MCSubtargetInfo::MCSubtargetInfo(const Triple &TT, StringRef C, StringRef FS,
208-
ArrayRef<SubtargetFeatureKV> PF,
222+
MCSubtargetInfo::MCSubtargetInfo(const Triple &TT, StringRef C, StringRef TC,
223+
StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
209224
ArrayRef<SubtargetSubTypeKV> PD,
210225
const MCWriteProcResEntry *WPR,
211226
const MCWriteLatencyEntry *WL,
212227
const MCReadAdvanceEntry *RA,
213228
const InstrStage *IS, const unsigned *OC,
214229
const unsigned *FP)
215-
: TargetTriple(TT), CPU(std::string(C)), ProcFeatures(PF), ProcDesc(PD),
216-
WriteProcResTable(WPR), WriteLatencyTable(WL), ReadAdvanceTable(RA),
217-
Stages(IS), OperandCycles(OC), ForwardingPaths(FP) {
218-
InitMCProcessorInfo(CPU, FS);
230+
: TargetTriple(TT), CPU(std::string(C)), TuneCPU(std::string(TC)),
231+
ProcFeatures(PF), ProcDesc(PD), WriteProcResTable(WPR),
232+
WriteLatencyTable(WL), ReadAdvanceTable(RA), Stages(IS),
233+
OperandCycles(OC), ForwardingPaths(FP) {
234+
InitMCProcessorInfo(CPU, TuneCPU, FS);
219235
}
220236

221237
FeatureBitset MCSubtargetInfo::ToggleFeature(uint64_t FB) {

‎llvm/lib/Target/AArch64/AArch64Subtarget.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,7 @@ AArch64Subtarget::initializeSubtargetDependencies(StringRef FS,
6767
if (CPUString.empty())
6868
CPUString = "generic";
6969

70-
ParseSubtargetFeatures(CPUString, FS);
70+
ParseSubtargetFeatures(CPUString, /*TuneCPU*/ CPUString, FS);
7171
initializeProperties();
7272

7373
return *this;
@@ -200,7 +200,7 @@ void AArch64Subtarget::initializeProperties() {
200200
AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
201201
const std::string &FS,
202202
const TargetMachine &TM, bool LittleEndian)
203-
: AArch64GenSubtargetInfo(TT, CPU, FS),
203+
: AArch64GenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
204204
ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
205205
CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
206206
IsLittle(LittleEndian),

‎llvm/lib/Target/AArch64/AArch64Subtarget.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -511,7 +511,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
511511

512512
/// ParseSubtargetFeatures - Parses features string setting specified
513513
/// subtarget options. Definition of function is auto generated by tblgen.
514-
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
514+
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
515515

516516
/// ClassifyGlobalReference - Find the target operand flags that describe
517517
/// how a global value should be referenced for the current subtarget.

‎llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5160,7 +5160,8 @@ bool AArch64AsmParser::parseDirectiveArch(SMLoc L) {
51605160

51615161
MCSubtargetInfo &STI = copySTI();
51625162
std::vector<std::string> ArchFeatures(AArch64Features.begin(), AArch64Features.end());
5163-
STI.setDefaultFeatures("generic", join(ArchFeatures.begin(), ArchFeatures.end(), ","));
5163+
STI.setDefaultFeatures("generic", /*TuneCPU*/ "generic",
5164+
join(ArchFeatures.begin(), ArchFeatures.end(), ","));
51645165

51655166
SmallVector<StringRef, 4> RequestedExtensions;
51665167
if (!ExtensionString.empty())
@@ -5262,7 +5263,7 @@ bool AArch64AsmParser::parseDirectiveCPU(SMLoc L) {
52625263
}
52635264

52645265
MCSubtargetInfo &STI = copySTI();
5265-
STI.setDefaultFeatures(CPU, "");
5266+
STI.setDefaultFeatures(CPU, /*TuneCPU*/ CPU, "");
52665267
CurLoc = incrementLoc(CurLoc, CPU.size());
52675268

52685269
ExpandCryptoAEK(llvm::AArch64::getCPUArchKind(CPU), RequestedExtensions);

‎llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@ createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
5353
if (CPU.empty())
5454
CPU = "generic";
5555

56-
return createAArch64MCSubtargetInfoImpl(TT, CPU, FS);
56+
return createAArch64MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
5757
}
5858

5959
void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {

‎llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@ R600Subtarget::initializeSubtargetDependencies(const Triple &TT,
5757
StringRef GPU, StringRef FS) {
5858
SmallString<256> FullFS("+promote-alloca,");
5959
FullFS += FS;
60-
ParseSubtargetFeatures(GPU, FullFS);
60+
ParseSubtargetFeatures(GPU, /*TuneCPU*/ GPU, FullFS);
6161

6262
HasMulU24 = getGeneration() >= EVERGREEN;
6363
HasMulI24 = hasCaymanISA();
@@ -97,7 +97,7 @@ GCNSubtarget::initializeSubtargetDependencies(const Triple &TT,
9797

9898
FullFS += FS;
9999

100-
ParseSubtargetFeatures(GPU, FullFS);
100+
ParseSubtargetFeatures(GPU, /*TuneCPU*/ GPU, FullFS);
101101

102102
// We don't support FP64 for EG/NI atm.
103103
assert(!hasFP64() || (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS));
@@ -170,7 +170,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT) :
170170

171171
GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
172172
const GCNTargetMachine &TM) :
173-
AMDGPUGenSubtargetInfo(TT, GPU, FS),
173+
AMDGPUGenSubtargetInfo(TT, GPU, /*TuneCPU*/ GPU, FS),
174174
AMDGPUSubtarget(TT),
175175
TargetTriple(TT),
176176
Gen(TT.getOS() == Triple::AMDHSA ? SEA_ISLANDS : SOUTHERN_ISLANDS),
@@ -541,7 +541,7 @@ unsigned AMDGPUSubtarget::getKernArgSegmentSize(const Function &F,
541541

542542
R600Subtarget::R600Subtarget(const Triple &TT, StringRef GPU, StringRef FS,
543543
const TargetMachine &TM) :
544-
R600GenSubtargetInfo(TT, GPU, FS),
544+
R600GenSubtargetInfo(TT, GPU, /*TuneCPU*/GPU, FS),
545545
AMDGPUSubtarget(TT),
546546
InstrInfo(*this),
547547
FrameLowering(TargetFrameLowering::StackGrowsUp, getStackAlignment(), 0),

‎llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -471,7 +471,7 @@ class GCNSubtarget : public AMDGPUGenSubtargetInfo,
471471
return &InstrItins;
472472
}
473473

474-
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
474+
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
475475

476476
Generation getGeneration() const {
477477
return (Generation)Gen;
@@ -1295,7 +1295,7 @@ class R600Subtarget final : public R600GenSubtargetInfo,
12951295
return &TSInfo;
12961296
}
12971297

1298-
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
1298+
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
12991299

13001300
Generation getGeneration() const {
13011301
return Gen;

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -74,8 +74,8 @@ MCRegisterInfo *llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour) {
7474
static MCSubtargetInfo *
7575
createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
7676
if (TT.getArch() == Triple::r600)
77-
return createR600MCSubtargetInfoImpl(TT, CPU, FS);
78-
return createAMDGPUMCSubtargetInfoImpl(TT, CPU, FS);
77+
return createR600MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
78+
return createAMDGPUMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
7979
}
8080

8181
static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,

‎llvm/lib/Target/ARM/ARMSubtarget.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -97,9 +97,9 @@ ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
9797
const std::string &FS,
9898
const ARMBaseTargetMachine &TM, bool IsLittle,
9999
bool MinSize)
100-
: ARMGenSubtargetInfo(TT, CPU, FS), UseMulOps(UseFusedMulOps),
101-
CPUString(CPU), OptMinSize(MinSize), IsLittle(IsLittle),
102-
TargetTriple(TT), Options(TM.Options), TM(TM),
100+
: ARMGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
101+
UseMulOps(UseFusedMulOps), CPUString(CPU), OptMinSize(MinSize),
102+
IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options), TM(TM),
103103
FrameLowering(initializeFrameLowering(CPU, FS)),
104104
// At this point initializeSubtargetDependencies has been called so
105105
// we can query directly.
@@ -185,7 +185,7 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
185185
else
186186
ArchFS = std::string(FS);
187187
}
188-
ParseSubtargetFeatures(CPUString, ArchFS);
188+
ParseSubtargetFeatures(CPUString, /*TuneCPU*/ CPUString, ArchFS);
189189

190190
// FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
191191
// Assert this for now to make the change obvious.

‎llvm/lib/Target/ARM/ARMSubtarget.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -526,7 +526,7 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
526526

527527
/// ParseSubtargetFeatures - Parses features string setting specified
528528
/// subtarget options. Definition of function is auto generated by tblgen.
529-
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
529+
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
530530

531531
/// initializeSubtargetDependencies - Initializes using a CPU and feature string
532532
/// so that we can use initializer lists for subtarget initialization.

‎llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11134,7 +11134,8 @@ bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
1113411134
bool WasThumb = isThumb();
1113511135
Triple T;
1113611136
MCSubtargetInfo &STI = copySTI();
11137-
STI.setDefaultFeatures("", ("+" + ARM::getArchName(ID)).str());
11137+
STI.setDefaultFeatures("", /*TuneCPU*/ "",
11138+
("+" + ARM::getArchName(ID)).str());
1113811139
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
1113911140
FixModeAfterArchChange(WasThumb, L);
1114011141

@@ -11247,7 +11248,7 @@ bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
1124711248

1124811249
bool WasThumb = isThumb();
1124911250
MCSubtargetInfo &STI = copySTI();
11250-
STI.setDefaultFeatures(CPU, "");
11251+
STI.setDefaultFeatures(CPU, /*TuneCPU*/ CPU, "");
1125111252
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
1125211253
FixModeAfterArchChange(WasThumb, L);
1125311254

‎llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -190,7 +190,7 @@ MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT,
190190
ArchFS = std::string(FS);
191191
}
192192

193-
return createARMMCSubtargetInfoImpl(TT, CPU, ArchFS);
193+
return createARMMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, ArchFS);
194194
}
195195

196196
static MCInstrInfo *createARMMCInstrInfo() {

‎llvm/lib/Target/AVR/AVRSubtarget.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@ namespace llvm {
2929

3030
AVRSubtarget::AVRSubtarget(const Triple &TT, const std::string &CPU,
3131
const std::string &FS, const AVRTargetMachine &TM)
32-
: AVRGenSubtargetInfo(TT, CPU, FS), ELFArch(0),
32+
: AVRGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), ELFArch(0),
3333

3434
// Subtarget features
3535
m_hasSRAM(false), m_hasJMPCALL(false), m_hasIJMPCALL(false),
@@ -43,14 +43,14 @@ AVRSubtarget::AVRSubtarget(const Triple &TT, const std::string &CPU,
4343
InstrInfo(), FrameLowering(),
4444
TLInfo(TM, initializeSubtargetDependencies(CPU, FS, TM)), TSInfo() {
4545
// Parse features string.
46-
ParseSubtargetFeatures(CPU, FS);
46+
ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS);
4747
}
4848

4949
AVRSubtarget &
5050
AVRSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
5151
const TargetMachine &TM) {
5252
// Parse features string.
53-
ParseSubtargetFeatures(CPU, FS);
53+
ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS);
5454
return *this;
5555
}
5656

0 commit comments

Comments
 (0)