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[VE] Remove output to /dev/stdout
Sending output to /dev/stdout on AIX gets an llc permission denied error, so this patch removes this from the tests. Reviewed By: simoll, hubert.reinterpretcast Differential Revision: https://reviews.llvm.org/D121799
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llvm/test/CodeGen/VE/Vector/vec_reduce_add.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
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; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
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declare i64 @llvm.vector.reduce.add.v256i64(<256 x i64>)
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llvm/test/CodeGen/VE/Vector/vec_reduce_and.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
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; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
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declare i64 @llvm.vector.reduce.and.v256i64(<256 x i64>)
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llvm/test/CodeGen/VE/Vector/vec_reduce_or.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
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; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
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declare i64 @llvm.vector.reduce.or.v256i64(<256 x i64>)
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llvm/test/CodeGen/VE/Vector/vec_reduce_smax.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
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; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
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declare i64 @llvm.vector.reduce.smax.v256i64(<256 x i64>)
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llvm/test/CodeGen/VE/Vector/vec_reduce_xor.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
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; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
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declare i64 @llvm.vector.reduce.xor.v256i64(<256 x i64>)
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llvm/test/CodeGen/VE/Vector/vp_reduce_add.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
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; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
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declare i64 @llvm.vp.reduce.add.v256i64(i64, <256 x i64>, <256 x i1>, i32)
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llvm/test/CodeGen/VE/Vector/vp_reduce_and.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
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; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
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declare i64 @llvm.vp.reduce.and.v256i64(i64, <256 x i64>, <256 x i1>, i32)
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llvm/test/CodeGen/VE/Vector/vp_reduce_or.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
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; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
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declare i64 @llvm.vp.reduce.or.v256i64(i64, <256 x i64>, <256 x i1>, i32)
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llvm/test/CodeGen/VE/Vector/vp_reduce_smax.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
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; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
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declare i64 @llvm.vp.reduce.smax.v256i64(i64, <256 x i64>, <256 x i1>, i32)
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llvm/test/CodeGen/VE/Vector/vp_reduce_xor.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s
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; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
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declare i64 @llvm.vp.reduce.xor.v256i64(i64, <256 x i64>, <256 x i1>, i32)
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