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[RISCV] Add a pass to merge moving parameter registers instructions for Zcmp
This patch adds a pass to generate `cm.mvsa01` & `cm.mva01s`. RISCVMoveOptimizer.cpp which combines two mv inst into one cm.mva01s or cm.mva01s. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D150415
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‎llvm/lib/Target/RISCV/CMakeLists.txt

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@@ -36,6 +36,7 @@ add_llvm_target(RISCVCodeGen
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RISCVMergeBaseOffset.cpp
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RISCVOptWInstrs.cpp
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RISCVRedundantCopyElimination.cpp
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RISCVMoveMerger.cpp
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RISCVRegisterInfo.cpp
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RISCVRVVInitUndef.cpp
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RISCVSubtarget.cpp

‎llvm/lib/Target/RISCV/RISCV.h

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@@ -70,6 +70,9 @@ FunctionPass *createRISCVInitUndefPass();
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void initializeRISCVInitUndefPass(PassRegistry &);
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extern char &RISCVInitUndefID;
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FunctionPass *createRISCVMoveMergePass();
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void initializeRISCVMoveMergePass(PassRegistry &);
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InstructionSelector *createRISCVInstructionSelector(const RISCVTargetMachine &,
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RISCVSubtarget &,
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RISCVRegisterBankInfo &);

‎llvm/lib/Target/RISCV/RISCVMoveMerger.cpp

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//===---------- RISCVMoveMerge.cpp - RISCV move merge pass -------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a pass that performs move related peephole optimizations
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// as Zcmp has specified. This pass should be run after register allocation.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVInstrInfo.h"
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#include "RISCVMachineFunctionInfo.h"
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using namespace llvm;
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#define RISCV_MOVE_MERGE_NAME "RISC-V Zcmp move merging pass"
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namespace {
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struct RISCVMoveMerge : public MachineFunctionPass {
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static char ID;
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RISCVMoveMerge() : MachineFunctionPass(ID) {
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initializeRISCVMoveMergePass(*PassRegistry::getPassRegistry());
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}
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const RISCVInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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// Track which register units have been modified and used.
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LiveRegUnits ModifiedRegUnits, UsedRegUnits;
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bool isCandidateToMergeMVA01S(const DestSourcePair &RegPair);
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bool isCandidateToMergeMVSA01(const DestSourcePair &RegPair);
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// Merge the two instructions indicated into a single pair instruction.
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MachineBasicBlock::iterator
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mergePairedInsns(MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator Paired, unsigned Opcode);
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// Look for C.MV instruction that can be combined with
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// the given instruction into CM.MVA01S or CM.MVSA01. Return the matching
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// instruction if one exists.
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MachineBasicBlock::iterator
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findMatchingInst(MachineBasicBlock::iterator &MBBI, unsigned InstOpcode,
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const DestSourcePair &RegPair);
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bool mergeMoveSARegPair(MachineBasicBlock &MBB);
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bool runOnMachineFunction(MachineFunction &Fn) override;
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StringRef getPassName() const override { return RISCV_MOVE_MERGE_NAME; }
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};
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char RISCVMoveMerge::ID = 0;
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} // end of anonymous namespace
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INITIALIZE_PASS(RISCVMoveMerge, "riscv-move-merge", RISCV_MOVE_MERGE_NAME,
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false, false)
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// Check if registers meet CM.MVA01S constraints.
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bool RISCVMoveMerge::isCandidateToMergeMVA01S(const DestSourcePair &RegPair) {
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Register Destination = RegPair.Destination->getReg();
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Register Source = RegPair.Source->getReg();
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// If destination is not a0 or a1.
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if ((Destination == RISCV::X10 || Destination == RISCV::X11) &&
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RISCV::SR07RegClass.contains(Source))
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return true;
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return false;
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}
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// Check if registers meet CM.MVSA01 constraints.
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bool RISCVMoveMerge::isCandidateToMergeMVSA01(const DestSourcePair &RegPair) {
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Register Destination = RegPair.Destination->getReg();
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Register Source = RegPair.Source->getReg();
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// If Source is s0 - s7.
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if ((Source == RISCV::X10 || Source == RISCV::X11) &&
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RISCV::SR07RegClass.contains(Destination))
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return true;
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return false;
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}
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MachineBasicBlock::iterator
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RISCVMoveMerge::mergePairedInsns(MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator Paired,
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unsigned Opcode) {
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const MachineOperand *Sreg1, *Sreg2;
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MachineBasicBlock::iterator E = I->getParent()->end();
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MachineBasicBlock::iterator NextI = next_nodbg(I, E);
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DestSourcePair FirstPair = TII->isCopyInstrImpl(*I).value();
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DestSourcePair PairedRegs = TII->isCopyInstrImpl(*Paired).value();
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Register ARegInFirstPair = Opcode == RISCV::CM_MVA01S
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? FirstPair.Destination->getReg()
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: FirstPair.Source->getReg();
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if (NextI == Paired)
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NextI = next_nodbg(NextI, E);
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DebugLoc DL = I->getDebugLoc();
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// The order of S-reg depends on which instruction holds A0, instead of
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// the order of register pair.
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// e,g.
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// mv a1, s1
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// mv a0, s2 => cm.mva01s s2,s1
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//
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// mv a0, s2
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// mv a1, s1 => cm.mva01s s2,s1
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bool StartWithX10 = ARegInFirstPair == RISCV::X10;
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if (Opcode == RISCV::CM_MVA01S) {
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Sreg1 = StartWithX10 ? FirstPair.Source : PairedRegs.Source;
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Sreg2 = StartWithX10 ? PairedRegs.Source : FirstPair.Source;
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} else {
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Sreg1 = StartWithX10 ? FirstPair.Destination : PairedRegs.Destination;
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Sreg2 = StartWithX10 ? PairedRegs.Destination : FirstPair.Destination;
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}
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BuildMI(*I->getParent(), I, DL, TII->get(Opcode)).add(*Sreg1).add(*Sreg2);
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I->eraseFromParent();
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Paired->eraseFromParent();
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return NextI;
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}
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MachineBasicBlock::iterator
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RISCVMoveMerge::findMatchingInst(MachineBasicBlock::iterator &MBBI,
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unsigned InstOpcode,
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const DestSourcePair &RegPair) {
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MachineBasicBlock::iterator E = MBBI->getParent()->end();
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// Track which register units have been modified and used between the first
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// insn and the second insn.
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ModifiedRegUnits.clear();
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UsedRegUnits.clear();
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for (MachineBasicBlock::iterator I = next_nodbg(MBBI, E); I != E;
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I = next_nodbg(I, E)) {
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MachineInstr &MI = *I;
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if (auto SecondPair = TII->isCopyInstrImpl(MI)) {
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Register SourceReg = SecondPair->Source->getReg();
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Register DestReg = SecondPair->Destination->getReg();
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if (InstOpcode == RISCV::CM_MVA01S &&
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isCandidateToMergeMVA01S(*SecondPair)) {
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// If register pair is valid and destination registers are different.
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if ((RegPair.Destination->getReg() == DestReg))
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return E;
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// If paired destination register was modified or used, the source reg
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// was modified, there is no possibility of finding matching
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// instruction so exit early.
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if (!ModifiedRegUnits.available(DestReg) ||
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!UsedRegUnits.available(DestReg) ||
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!ModifiedRegUnits.available(SourceReg))
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return E;
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return I;
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} else if (InstOpcode == RISCV::CM_MVSA01 &&
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isCandidateToMergeMVSA01(*SecondPair)) {
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if ((RegPair.Source->getReg() == SourceReg) ||
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(RegPair.Destination->getReg() == DestReg))
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return E;
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if (!ModifiedRegUnits.available(DestReg) ||
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!UsedRegUnits.available(DestReg) ||
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!ModifiedRegUnits.available(SourceReg))
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return E;
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return I;
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}
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}
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// Update modified / used register units.
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LiveRegUnits::accumulateUsedDefed(MI, ModifiedRegUnits, UsedRegUnits, TRI);
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}
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return E;
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}
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// Finds instructions, which could be represented as C.MV instructions and
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// merged into CM.MVA01S or CM.MVSA01.
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bool RISCVMoveMerge::mergeMoveSARegPair(MachineBasicBlock &MBB) {
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bool Modified = false;
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for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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MBBI != E;) {
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// Check if the instruction can be compressed to C.MV instruction. If it
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// can, return Dest/Src register pair.
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auto RegPair = TII->isCopyInstrImpl(*MBBI);
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if (RegPair.has_value()) {
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unsigned Opcode = 0;
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if (isCandidateToMergeMVA01S(*RegPair))
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Opcode = RISCV::CM_MVA01S;
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else if (isCandidateToMergeMVSA01(*RegPair))
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Opcode = RISCV::CM_MVSA01;
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else {
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++MBBI;
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continue;
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}
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MachineBasicBlock::iterator Paired =
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findMatchingInst(MBBI, Opcode, RegPair.value());
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// If matching instruction can be found merge them.
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if (Paired != E) {
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MBBI = mergePairedInsns(MBBI, Paired, Opcode);
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Modified = true;
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continue;
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}
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}
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++MBBI;
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}
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return Modified;
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}
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bool RISCVMoveMerge::runOnMachineFunction(MachineFunction &Fn) {
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if (skipFunction(Fn.getFunction()))
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return false;
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const RISCVSubtarget *Subtarget = &Fn.getSubtarget<RISCVSubtarget>();
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if (!Subtarget->hasStdExtZcmp())
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return false;
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TII = Subtarget->getInstrInfo();
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TRI = Subtarget->getRegisterInfo();
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// Resize the modified and used register unit trackers. We do this once
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// per function and then clear the register units each time we optimize a
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// move.
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ModifiedRegUnits.init(*TRI);
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UsedRegUnits.init(*TRI);
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bool Modified = false;
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for (auto &MBB : Fn)
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Modified |= mergeMoveSARegPair(MBB);
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return Modified;
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}
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/// createRISCVMoveMergePass - returns an instance of the
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/// move merge pass.
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FunctionPass *llvm::createRISCVMoveMergePass() { return new RISCVMoveMerge(); }

‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

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@@ -87,6 +87,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
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initializeRISCVInsertReadWriteCSRPass(*PR);
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initializeRISCVDAGToDAGISelPass(*PR);
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initializeRISCVInitUndefPass(*PR);
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initializeRISCVMoveMergePass(*PR);
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}
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static StringRef computeDataLayout(const Triple &TT) {
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}
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void RISCVPassConfig::addPreEmitPass2() {
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if (TM->getOptLevel() != CodeGenOpt::None)
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addPass(createRISCVMoveMergePass());
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addPass(createRISCVExpandPseudoPass());
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// Schedule the expansion of AMOs at the last possible moment, avoiding the

‎llvm/test/CodeGen/RISCV/O3-pipeline.ll

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; CHECK-NEXT: Lazy Machine Block Frequency Analysis
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; CHECK-NEXT: Machine Optimization Remark Emitter
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; CHECK-NEXT: Stack Frame Layout Analysis
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; CHECK-NEXT: RISC-V Zcmp move merging pass
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; CHECK-NEXT: RISC-V pseudo instruction expansion pass
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; CHECK-NEXT: RISC-V atomic pseudo instruction expansion pass
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; CHECK-NEXT: Lazy Machine Block Frequency Analysis

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