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[HLSL] Make sure isSigned flag is set on target type for TypedBuffer resources with signed int vectors (llvm#130223)
Fixes llvm#130191
1 parent f333841 commit cb64a36

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2 files changed

+12
-5
lines changed

2 files changed

+12
-5
lines changed

clang/lib/CodeGen/Targets/DirectX.cpp

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -59,8 +59,14 @@ llvm::Type *DirectXTargetCodeGenInfo::getHLSLType(
5959
SmallVector<unsigned, 3> Ints = {/*IsWriteable*/ ResAttrs.ResourceClass ==
6060
llvm::dxil::ResourceClass::UAV,
6161
/*IsROV*/ ResAttrs.IsROV};
62-
if (!ResAttrs.RawBuffer)
63-
Ints.push_back(/*IsSigned*/ ContainedTy->isSignedIntegerType());
62+
if (!ResAttrs.RawBuffer) {
63+
const clang::Type *ElemType = ContainedTy->getUnqualifiedDesugaredType();
64+
if (ElemType->isVectorType())
65+
ElemType = cast<clang::VectorType>(ElemType)
66+
->getElementType()
67+
->getUnqualifiedDesugaredType();
68+
Ints.push_back(/*IsSigned*/ ElemType->isSignedIntegerType());
69+
}
6470

6571
return llvm::TargetExtType::get(Ctx, TypeName, {ElemType}, Ints);
6672
}

clang/test/CodeGenHLSL/builtins/RWBuffer-elementtype.hlsl

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -10,10 +10,11 @@
1010
// DXIL: %"class.hlsl::RWBuffer.5" = type { target("dx.TypedBuffer", half, 1, 0, 0) }
1111
// DXIL: %"class.hlsl::RWBuffer.6" = type { target("dx.TypedBuffer", float, 1, 0, 0) }
1212
// DXIL: %"class.hlsl::RWBuffer.7" = type { target("dx.TypedBuffer", double, 1, 0, 0) }
13-
// DXIL: %"class.hlsl::RWBuffer.8" = type { target("dx.TypedBuffer", <4 x i16>, 1, 0, 0) }
13+
// DXIL: %"class.hlsl::RWBuffer.8" = type { target("dx.TypedBuffer", <4 x i16>, 1, 0, 1) }
1414
// DXIL: %"class.hlsl::RWBuffer.9" = type { target("dx.TypedBuffer", <3 x i32>, 1, 0, 0) }
1515
// DXIL: %"class.hlsl::RWBuffer.10" = type { target("dx.TypedBuffer", <2 x half>, 1, 0, 0) }
1616
// DXIL: %"class.hlsl::RWBuffer.11" = type { target("dx.TypedBuffer", <3 x float>, 1, 0, 0) }
17+
// DXIL: %"class.hlsl::RWBuffer.12" = type { target("dx.TypedBuffer", <4 x i32>, 1, 0, 1) }
1718

1819
// SPIRV: %"class.hlsl::RWBuffer" = type { target("spirv.Image", i16, 5, 2, 0, 0, 2, 0) }
1920
// SPIRV: %"class.hlsl::RWBuffer.0" = type { target("spirv.Image", i16, 5, 2, 0, 0, 2, 0) }
@@ -28,8 +29,7 @@
2829
// SPIRV: %"class.hlsl::RWBuffer.9" = type { target("spirv.Image", i32, 5, 2, 0, 0, 2, 0) }
2930
// SPIRV: %"class.hlsl::RWBuffer.10" = type { target("spirv.Image", half, 5, 2, 0, 0, 2, 0) }
3031
// SPIRV: %"class.hlsl::RWBuffer.11" = type { target("spirv.Image", float, 5, 2, 0, 0, 2, 0) }
31-
32-
32+
// SPIRV: %"class.hlsl::RWBuffer.12" = type { target("spirv.Image", i32, 5, 2, 0, 0, 2, 0) }
3333

3434
RWBuffer<int16_t> BufI16;
3535
RWBuffer<uint16_t> BufU16;
@@ -44,6 +44,7 @@ RWBuffer< vector<int16_t, 4> > BufI16x4;
4444
RWBuffer< vector<uint, 3> > BufU32x3;
4545
RWBuffer<half2> BufF16x2;
4646
RWBuffer<float3> BufF32x3;
47+
RWBuffer<int4> BufI32x4;
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// TODO: RWBuffer<snorm half> BufSNormF16; -> 11
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// TODO: RWBuffer<unorm half> BufUNormF16; -> 12
4950
// TODO: RWBuffer<snorm float> BufSNormF32; -> 13

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