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kazutakahiratakazutakahirata
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Use APInt::popcount instead of APInt::countPopulation (NFC)
This is for consistency with the C++20-style bit manipulation functions in <bit>.
1 parent 179a24c commit cbde212

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21 files changed

+44
-49
lines changed

21 files changed

+44
-49
lines changed

‎clang/lib/AST/ExprConstant.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12142,7 +12142,7 @@ bool IntExprEvaluator::VisitBuiltinCallExpr(const CallExpr *E,
1214212142
if (!EvaluateInteger(E->getArg(0), Val, Info))
1214312143
return false;
1214412144

12145-
return Success(Val.countPopulation() % 2, E);
12145+
return Success(Val.popcount() % 2, E);
1214612146
}
1214712147

1214812148
case Builtin::BI__builtin_popcount:
@@ -12152,7 +12152,7 @@ bool IntExprEvaluator::VisitBuiltinCallExpr(const CallExpr *E,
1215212152
if (!EvaluateInteger(E->getArg(0), Val, Info))
1215312153
return false;
1215412154

12155-
return Success(Val.countPopulation(), E);
12155+
return Success(Val.popcount(), E);
1215612156
}
1215712157

1215812158
case Builtin::BI__builtin_rotateleft8:

‎llvm/include/llvm/ADT/APInt.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -347,7 +347,7 @@ class [[nodiscard]] APInt {
347347
///
348348
/// \returns true if this APInt only has the specified bit set.
349349
bool isOneBitSet(unsigned BitNo) const {
350-
return (*this)[BitNo] && countPopulation() == 1;
350+
return (*this)[BitNo] && popcount() == 1;
351351
}
352352

353353
/// Determine if all bits are set. This is true for zero-width values.

‎llvm/include/llvm/CodeGen/BasicTTIImpl.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1508,7 +1508,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
15081508
// SelectionDAGBuilder.
15091509
APInt Exponent = RHSC->getValue().abs();
15101510
unsigned ActiveBits = Exponent.getActiveBits();
1511-
unsigned PopCount = Exponent.countPopulation();
1511+
unsigned PopCount = Exponent.popcount();
15121512
InstructionCost Cost = (ActiveBits + PopCount - 2) *
15131513
thisT()->getArithmeticInstrCost(
15141514
Instruction::FMul, RetTy, CostKind);

‎llvm/include/llvm/Support/KnownBits.h

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@ struct KnownBits {
4949
/// Returns true if we know the value of all bits.
5050
bool isConstant() const {
5151
assert(!hasConflict() && "KnownBits conflict!");
52-
return Zero.countPopulation() + One.countPopulation() == getBitWidth();
52+
return Zero.popcount() + One.popcount() == getBitWidth();
5353
}
5454

5555
/// Returns the value when all bits have a known value. This just returns One
@@ -290,13 +290,11 @@ struct KnownBits {
290290
}
291291

292292
/// Returns the number of bits known to be one.
293-
unsigned countMinPopulation() const {
294-
return One.countPopulation();
295-
}
293+
unsigned countMinPopulation() const { return One.popcount(); }
296294

297295
/// Returns the maximum number of bits that could be one.
298296
unsigned countMaxPopulation() const {
299-
return getBitWidth() - Zero.countPopulation();
297+
return getBitWidth() - Zero.popcount();
300298
}
301299

302300
/// Returns the maximum number of bits needed to represent all possible

‎llvm/lib/Analysis/ConstantFolding.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2395,7 +2395,7 @@ static Constant *ConstantFoldScalarCall1(StringRef Name,
23952395
case Intrinsic::bswap:
23962396
return ConstantInt::get(Ty->getContext(), Op->getValue().byteSwap());
23972397
case Intrinsic::ctpop:
2398-
return ConstantInt::get(Ty, Op->getValue().countPopulation());
2398+
return ConstantInt::get(Ty, Op->getValue().popcount());
23992399
case Intrinsic::bitreverse:
24002400
return ConstantInt::get(Ty->getContext(), Op->getValue().reverseBits());
24012401
case Intrinsic::convert_from_fp16: {

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -18187,7 +18187,7 @@ struct LoadedSlice {
1818718187

1818818188
/// Get the size of the slice to be loaded in bytes.
1818918189
unsigned getLoadedSize() const {
18190-
unsigned SliceSize = getUsedBits().countPopulation();
18190+
unsigned SliceSize = getUsedBits().popcount();
1819118191
assert(!(SliceSize & 0x7) && "Size is not a multiple of a byte.");
1819218192
return SliceSize / 8;
1819318193
}
@@ -24034,7 +24034,7 @@ static SDValue combineShuffleOfSplatVal(ShuffleVectorSDNode *Shuf,
2403424034
assert((unsigned)Idx < NumElts && "Out-of-bounds shuffle indice?");
2403524035
DemandedElts.setBit(Idx);
2403624036
}
24037-
assert(DemandedElts.countPopulation() > 1 && "Is a splat shuffle already?");
24037+
assert(DemandedElts.popcount() > 1 && "Is a splat shuffle already?");
2403824038
APInt UndefElts;
2403924039
if (DAG.isSplatValue(Shuf->getOperand(0), DemandedElts, UndefElts)) {
2404024040
// Even if all demanded elements are splat, some of them could be undef.
@@ -26109,7 +26109,7 @@ SDValue DAGCombiner::SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
2610926109
N0->getValueType(0) == VT && isNullConstant(N1) && isNullConstant(N2)) {
2611026110
SDValue AndLHS = N0->getOperand(0);
2611126111
auto *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
26112-
if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
26112+
if (ConstAndRHS && ConstAndRHS->getAPIntValue().popcount() == 1) {
2611326113
// Shift the tested bit over the sign bit.
2611426114
const APInt &AndMask = ConstAndRHS->getAPIntValue();
2611526115
unsigned ShCt = AndMask.getBitWidth() - 1;

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2714,7 +2714,7 @@ bool SelectionDAG::isSplatValue(SDValue V, const APInt &DemandedElts,
27142714
// TODO: Handle source ops splats with undefs.
27152715
auto CheckSplatSrc = [&](SDValue Src, const APInt &SrcElts) {
27162716
APInt SrcUndefs;
2717-
return (SrcElts.countPopulation() == 1) ||
2717+
return (SrcElts.popcount() == 1) ||
27182718
(isSplatValue(Src, SrcElts, SrcUndefs, Depth + 1) &&
27192719
(SrcElts & SrcUndefs).isZero());
27202720
};
@@ -5264,7 +5264,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
52645264
return getConstant(Val.byteSwap(), DL, VT, C->isTargetOpcode(),
52655265
C->isOpaque());
52665266
case ISD::CTPOP:
5267-
return getConstant(Val.countPopulation(), DL, VT, C->isTargetOpcode(),
5267+
return getConstant(Val.popcount(), DL, VT, C->isTargetOpcode(),
52685268
C->isOpaque());
52695269
case ISD::CTLZ:
52705270
case ISD::CTLZ_ZERO_UNDEF:

‎llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3149,7 +3149,7 @@ static bool tryBitfieldInsertOpFromOrAndImm(SDNode *N, SelectionDAG *CurDAG) {
31493149

31503150
// BFI/BFXIL dst, src, #lsb, #width.
31513151
int LSB = llvm::countr_one(NotKnownZero);
3152-
int Width = BitWidth - APInt(BitWidth, NotKnownZero).countPopulation();
3152+
int Width = BitWidth - APInt(BitWidth, NotKnownZero).popcount();
31533153

31543154
// BFI/BFXIL is an alias of BFM, so translate to BFM operands.
31553155
unsigned ImmR = (BitWidth - LSB) % BitWidth;
@@ -3505,7 +3505,7 @@ static bool tryBitfieldInsertOpFromOr(SDNode *N, const APInt &UsefulBits,
35053505
SDValue Src = And1->getOperand(0);
35063506
SDValue Dst = And0->getOperand(0);
35073507
unsigned LSB = llvm::countr_zero(Mask1Imm);
3508-
int Width = BitWidth - APInt(BitWidth, Mask0Imm).countPopulation();
3508+
int Width = BitWidth - APInt(BitWidth, Mask0Imm).popcount();
35093509

35103510
// The BFXIL inserts the low-order bits from a source register, so right
35113511
// shift the needed bits into place.

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2115,7 +2115,7 @@ bool AArch64TargetLowering::targetShrinkDemandedConstant(
21152115
"i32 or i64 is expected after legalization.");
21162116

21172117
// Exit early if we demand all bits.
2118-
if (DemandedBits.countPopulation() == Size)
2118+
if (DemandedBits.popcount() == Size)
21192119
return false;
21202120

21212121
unsigned NewOpc;

‎llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1152,7 +1152,7 @@ static Value *simplifyAMDGCNMemoryIntrinsicDemanded(InstCombiner &IC,
11521152
Args[DMaskIdx] = ConstantInt::get(DMask->getType(), NewDMaskVal);
11531153
}
11541154

1155-
unsigned NewNumElts = DemandedElts.countPopulation();
1155+
unsigned NewNumElts = DemandedElts.popcount();
11561156
if (!NewNumElts)
11571157
return UndefValue::get(IIVTy);
11581158

‎llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5031,7 +5031,7 @@ void AMDGPUInstructionSelector::renderPopcntImm(MachineInstrBuilder &MIB,
50315031
int OpIdx) const {
50325032
assert(MI.getOpcode() == TargetOpcode::G_CONSTANT && OpIdx == -1 &&
50335033
"Expected G_CONSTANT");
5034-
MIB.addImm(MI.getOperand(1).getCImm()->getValue().countPopulation());
5034+
MIB.addImm(MI.getOperand(1).getCImm()->getValue().popcount());
50355035
}
50365036

50375037
/// This only really exists to satisfy DAG type checking machinery, so is a

‎llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3542,7 +3542,7 @@ static std::optional<std::pair<unsigned, unsigned>>
35423542
getContiguousRangeOfSetBits(const APInt &A) {
35433543
unsigned FirstOne = A.getBitWidth() - A.countLeadingZeros() - 1;
35443544
unsigned LastOne = A.countTrailingZeros();
3545-
if (A.countPopulation() != (FirstOne - LastOne + 1))
3545+
if (A.popcount() != (FirstOne - LastOne + 1))
35463546
return std::nullopt;
35473547
return std::make_pair(FirstOne, LastOne);
35483548
}

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14687,7 +14687,7 @@ static SDValue ParseBFI(SDNode *N, APInt &ToMask, APInt &FromMask) {
1468714687

1468814688
SDValue From = N->getOperand(1);
1468914689
ToMask = ~cast<ConstantSDNode>(N->getOperand(2))->getAPIntValue();
14690-
FromMask = APInt::getLowBitsSet(ToMask.getBitWidth(), ToMask.countPopulation());
14690+
FromMask = APInt::getLowBitsSet(ToMask.getBitWidth(), ToMask.popcount());
1469114691

1469214692
// If the Base came from a SHR #C, we can deduce that it is really testing bit
1469314693
// #C in the base of the SHR.
@@ -17915,7 +17915,7 @@ SDValue ARMTargetLowering::PerformCMOVToBFICombine(SDNode *CMOV, SelectionDAG &D
1791517915
// Now, is it profitable to continue?
1791617916
APInt OrCI = OrC->getAPIntValue();
1791717917
unsigned Heuristic = Subtarget->isThumb() ? 3 : 2;
17918-
if (OrCI.countPopulation() > Heuristic)
17918+
if (OrCI.popcount() > Heuristic)
1791917919
return SDValue();
1792017920

1792117921
// Lastly, can we determine that the bits defined by OrCI

‎llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -670,8 +670,7 @@ bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
670670
// as the original value.
671671
if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
672672

673-
Imm = CurDAG->getTargetConstant(ImmValue.countPopulation() - 1, SDLoc(N),
674-
EltTy);
673+
Imm = CurDAG->getTargetConstant(ImmValue.popcount() - 1, SDLoc(N), EltTy);
675674
return true;
676675
}
677676
}
@@ -702,8 +701,7 @@ bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
702701
// Extract the run of set bits starting with bit zero, and test that the
703702
// result is the same as the original value
704703
if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
705-
Imm = CurDAG->getTargetConstant(ImmValue.countPopulation() - 1, SDLoc(N),
706-
EltTy);
704+
Imm = CurDAG->getTargetConstant(ImmValue.popcount() - 1, SDLoc(N), EltTy);
707705
return true;
708706
}
709707
}

‎llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -9401,14 +9401,14 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
94019401
LoadMask.setBit(i);
94029402
LastLoadedElt = i;
94039403
}
9404-
assert((ZeroMask.countPopulation() + UndefMask.countPopulation() +
9405-
LoadMask.countPopulation()) == NumElems &&
9404+
assert((ZeroMask.popcount() + UndefMask.popcount() + LoadMask.popcount()) ==
9405+
NumElems &&
94069406
"Incomplete element masks");
94079407

94089408
// Handle Special Cases - all undef or undef/zero.
9409-
if (UndefMask.countPopulation() == NumElems)
9409+
if (UndefMask.popcount() == NumElems)
94109410
return DAG.getUNDEF(VT);
9411-
if ((ZeroMask.countPopulation() + UndefMask.countPopulation()) == NumElems)
9411+
if ((ZeroMask.popcount() + UndefMask.popcount()) == NumElems)
94129412
return VT.isInteger() ? DAG.getConstant(0, DL, VT)
94139413
: DAG.getConstantFP(0.0, DL, VT);
94149414

@@ -11269,7 +11269,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
1126911269
// our source BUILD_VECTOR, create another FREEZE-UNDEF splat BUILD_VECTOR,
1127011270
// and blend the FREEZE-UNDEF operands back in.
1127111271
// FIXME: is this worthwhile even for a single FREEZE-UNDEF operand?
11272-
if (unsigned NumFrozenUndefElts = FrozenUndefMask.countPopulation();
11272+
if (unsigned NumFrozenUndefElts = FrozenUndefMask.popcount();
1127311273
NumFrozenUndefElts >= 2 && NumFrozenUndefElts < NumElems) {
1127411274
SmallVector<int, 16> BlendMask(NumElems, -1);
1127511275
SmallVector<SDValue, 16> Elts(NumElems, DAG.getUNDEF(OpEltVT));
@@ -11320,8 +11320,8 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
1132011320
if (SDValue BitOp = lowerBuildVectorToBitOp(BV, Subtarget, DAG))
1132111321
return BitOp;
1132211322

11323-
unsigned NumZero = ZeroMask.countPopulation();
11324-
unsigned NumNonZero = NonZeroMask.countPopulation();
11323+
unsigned NumZero = ZeroMask.popcount();
11324+
unsigned NumNonZero = NonZeroMask.popcount();
1132511325

1132611326
// If we are inserting one variable into a vector of non-zero constants, try
1132711327
// to avoid loading each constant element as a scalar. Load the constants as a
@@ -38089,7 +38089,7 @@ void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
3808938089
case X86ISD::PEXT: {
3809038090
Known = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
3809138091
// The result has as many leading zeros as the number of zeroes in the mask.
38092-
unsigned Count = Known.Zero.countPopulation();
38092+
unsigned Count = Known.Zero.popcount();
3809338093
Known.Zero = APInt::getHighBitsSet(BitWidth, Count);
3809438094
Known.One.clearAllBits();
3809538095
break;
@@ -43298,7 +43298,7 @@ bool X86TargetLowering::SimplifyDemandedBitsForTargetNode(
4329843298
// operand 0 used. Undemanded bits from the mask don't matter so filter
4329943299
// them before counting.
4330043300
KnownBits Known2;
43301-
uint64_t Count = (~Known.Zero & LoMask).countPopulation();
43301+
uint64_t Count = (~Known.Zero & LoMask).popcount();
4330243302
APInt DemandedMask(APInt::getLowBitsSet(BitWidth, Count));
4330343303
if (SimplifyDemandedBits(Op0, DemandedMask, Known2, TLO, Depth + 1))
4330443304
return true;
@@ -43411,7 +43411,7 @@ SDValue X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(
4341143411
if (IdentityOp == 0)
4341243412
break;
4341343413
}
43414-
assert((IdentityOp == 0 || IdentityOp.countPopulation() == 1) &&
43414+
assert((IdentityOp == 0 || IdentityOp.popcount() == 1) &&
4341543415
"Multiple identity shuffles detected");
4341643416

4341743417
if (IdentityOp != 0)

‎llvm/lib/Target/X86/X86TargetTransformInfo.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4502,7 +4502,7 @@ X86TTIImpl::getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts,
45024502
// series of UNPCK followed by CONCAT_VECTORS - all of these can be
45034503
// considered cheap.
45044504
if (Ty->isIntOrIntVectorTy())
4505-
Cost += DemandedElts.countPopulation();
4505+
Cost += DemandedElts.popcount();
45064506

45074507
// Get the smaller of the legalized or original pow2-extended number of
45084508
// vector elements, which represents the number of unpacks we'll end up
@@ -4667,7 +4667,7 @@ X86TTIImpl::getReplicationShuffleCost(Type *EltTy, int ReplicationFactor,
46674667
// then we won't need to do that shuffle, so adjust the cost accordingly.
46684668
APInt DemandedDstVectors = APIntOps::ScaleBitMask(
46694669
DemandedDstElts.zext(NumDstVectors * NumEltsPerDstVec), NumDstVectors);
4670-
unsigned NumDstVectorsDemanded = DemandedDstVectors.countPopulation();
4670+
unsigned NumDstVectorsDemanded = DemandedDstVectors.popcount();
46714671

46724672
InstructionCost SingleShuffleCost = getShuffleCost(
46734673
TTI::SK_PermuteSingleSrc, SingleDstVecTy, /*Mask=*/std::nullopt, CostKind,
@@ -4813,7 +4813,7 @@ InstructionCost X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
48134813
APInt DemandedElts =
48144814
APInt::getBitsSet(CoalescedVecTy->getNumElements(),
48154815
CoalescedVecEltIdx, CoalescedVecEltIdx + 1);
4816-
assert(DemandedElts.countPopulation() == 1 && "Inserting single value");
4816+
assert(DemandedElts.popcount() == 1 && "Inserting single value");
48174817
Cost += getScalarizationOverhead(CoalescedVecTy, DemandedElts, IsLoad,
48184818
!IsLoad, CostKind);
48194819
}

‎llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1653,7 +1653,7 @@ Value *InstCombinerImpl::SimplifyDemandedVectorElts(Value *V,
16531653
// corresponding input elements are undef.
16541654
for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx) {
16551655
APInt SubUndef = UndefElts2.lshr(OutIdx * Ratio).zextOrTrunc(Ratio);
1656-
if (SubUndef.countPopulation() == Ratio)
1656+
if (SubUndef.popcount() == Ratio)
16571657
UndefElts.setBit(OutIdx);
16581658
}
16591659
} else {

‎llvm/lib/Transforms/Utils/Local.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3152,7 +3152,7 @@ collectBitParts(Value *V, bool MatchBSwaps, bool MatchBitReversals,
31523152

31533153
// Check that the mask allows a multiple of 8 bits for a bswap, for an
31543154
// early exit.
3155-
unsigned NumMaskedBits = AndMask.countPopulation();
3155+
unsigned NumMaskedBits = AndMask.popcount();
31563156
if (!MatchBitReversals && (NumMaskedBits % 8) != 0)
31573157
return Result;
31583158

‎llvm/lib/Transforms/Utils/SimplifyCFG.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5469,7 +5469,7 @@ static bool eliminateDeadSwitchCases(SwitchInst *SI, DomTreeUpdater *DTU,
54695469
bool HasDefault =
54705470
!isa<UnreachableInst>(SI->getDefaultDest()->getFirstNonPHIOrDbg());
54715471
const unsigned NumUnknownBits =
5472-
Known.getBitWidth() - (Known.Zero | Known.One).countPopulation();
5472+
Known.getBitWidth() - (Known.Zero | Known.One).popcount();
54735473
assert(NumUnknownBits <= Known.getBitWidth());
54745474
if (HasDefault && DeadCases.empty() &&
54755475
NumUnknownBits < 64 /* avoid overflow */ &&
@@ -5860,7 +5860,7 @@ static Value *foldSwitchToSelect(const SwitchCaseResultVectorTy &ResultVector,
58605860

58615861
// Check if cases with the same result can cover all number
58625862
// in touched bits.
5863-
if (BitMask.countPopulation() == Log2_32(CaseCount)) {
5863+
if (BitMask.popcount() == Log2_32(CaseCount)) {
58645864
if (!MinCaseVal->isNullValue())
58655865
Condition = Builder.CreateSub(Condition, MinCaseVal);
58665866
Value *And = Builder.CreateAnd(Condition, ~BitMask, "switch.and");

‎llvm/utils/TableGen/CodeGenSchedule.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -370,8 +370,8 @@ processSTIPredicate(STIPredicateFunction &Fn,
370370
const std::pair<APInt, APInt> &RhsMasks = OpcodeMasks[RhsIdx];
371371

372372
auto LessThan = [](const APInt &Lhs, const APInt &Rhs) {
373-
unsigned LhsCountPopulation = Lhs.countPopulation();
374-
unsigned RhsCountPopulation = Rhs.countPopulation();
373+
unsigned LhsCountPopulation = Lhs.popcount();
374+
unsigned RhsCountPopulation = Rhs.popcount();
375375
return ((LhsCountPopulation < RhsCountPopulation) ||
376376
((LhsCountPopulation == RhsCountPopulation) &&
377377
(Lhs.countLeadingZeros() > Rhs.countLeadingZeros())));

‎mlir/lib/Dialect/Math/IR/MathOps.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -171,9 +171,8 @@ OpFoldResult math::CountTrailingZerosOp::fold(FoldAdaptor adaptor) {
171171

172172
OpFoldResult math::CtPopOp::fold(FoldAdaptor adaptor) {
173173
return constFoldUnaryOp<IntegerAttr>(
174-
adaptor.getOperands(), [](const APInt &a) {
175-
return APInt(a.getBitWidth(), a.countPopulation());
176-
});
174+
adaptor.getOperands(),
175+
[](const APInt &a) { return APInt(a.getBitWidth(), a.popcount()); });
177176
}
178177

179178
//===----------------------------------------------------------------------===//

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