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[ARM] Always enable UseAA in the arm backend
This feature controls whether AA is used into the backend, and was previously turned on for certain subtargets to help create less constrained scheduling graphs. This patch turns it on for all subtargets, so that they can all make use of the extra information to produce better code. Differential Revision: https://reviews.llvm.org/D69796
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6 files changed

+47
-36
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‎llvm/lib/Target/ARM/ARM.td

Lines changed: 1 addition & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -415,10 +415,6 @@ def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler",
415415
"DisablePostRAScheduler", "true",
416416
"Don't schedule again after register allocation">;
417417

418-
// Enable use of alias analysis during code generation
419-
def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
420-
"Use alias analysis during codegen">;
421-
422418
// Armv8.5-A extensions
423419

424420
def FeatureSB : SubtargetFeature<"sb", "HasSB", "true",
@@ -584,7 +580,6 @@ def ProcExynos : SubtargetFeature<"exynos", "ARMProcFamily", "Exynos",
584580
"Samsung Exynos processors",
585581
[FeatureZCZeroing,
586582
FeatureUseWideStrideVFP,
587-
FeatureUseAA,
588583
FeatureSplatVFPToNeon,
589584
FeatureSlowVGETLNi32,
590585
FeatureSlowVDUP32,
@@ -1067,21 +1062,18 @@ def : ProcessorModel<"cortex-m3", CortexM4Model, [ARMv7m,
10671062
ProcM3,
10681063
FeaturePrefLoopAlign32,
10691064
FeatureUseMISched,
1070-
FeatureUseAA,
10711065
FeatureHasNoBranchPredictor]>;
10721066

10731067
def : ProcessorModel<"sc300", CortexM4Model, [ARMv7m,
10741068
ProcM3,
10751069
FeatureUseMISched,
1076-
FeatureUseAA,
10771070
FeatureHasNoBranchPredictor]>;
10781071

10791072
def : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em,
10801073
FeatureVFP4_D16_SP,
10811074
FeaturePrefLoopAlign32,
10821075
FeatureHasSlowFPVMLx,
10831076
FeatureUseMISched,
1084-
FeatureUseAA,
10851077
FeatureHasNoBranchPredictor]>;
10861078

10871079
def : ProcNoItin<"cortex-m7", [ARMv7em,
@@ -1096,7 +1088,6 @@ def : ProcessorModel<"cortex-m33", CortexM4Model, [ARMv8mMainline,
10961088
FeaturePrefLoopAlign32,
10971089
FeatureHasSlowFPVMLx,
10981090
FeatureUseMISched,
1099-
FeatureUseAA,
11001091
FeatureHasNoBranchPredictor]>;
11011092

11021093
def : ProcessorModel<"cortex-m35p", CortexM4Model, [ARMv8mMainline,
@@ -1105,7 +1096,6 @@ def : ProcessorModel<"cortex-m35p", CortexM4Model, [ARMv8mMainline,
11051096
FeaturePrefLoopAlign32,
11061097
FeatureHasSlowFPVMLx,
11071098
FeatureUseMISched,
1108-
FeatureUseAA,
11091099
FeatureHasNoBranchPredictor]>;
11101100

11111101

@@ -1213,8 +1203,7 @@ def : ProcNoItin<"kryo", [ARMv8a, ProcKryo,
12131203

12141204
def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52,
12151205
FeatureUseMISched,
1216-
FeatureFPAO,
1217-
FeatureUseAA]>;
1206+
FeatureFPAO]>;
12181207

12191208
//===----------------------------------------------------------------------===//
12201209
// Register File Description

‎llvm/lib/Target/ARM/ARMSubtarget.h

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -223,9 +223,6 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
223223
/// register allocation.
224224
bool DisablePostRAScheduler = false;
225225

226-
/// UseAA - True if using AA during codegen (DAGCombine, MISched, etc)
227-
bool UseAA = false;
228-
229226
/// HasThumb2 - True if Thumb2 instructions are supported.
230227
bool HasThumb2 = false;
231228

@@ -811,7 +808,7 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
811808

812809
/// Enable use of alias analysis during code generation (during MI
813810
/// scheduling, DAGCombine, etc.).
814-
bool useAA() const override { return UseAA; }
811+
bool useAA() const override { return true; }
815812

816813
// enableAtomicExpand- True if we need to expand our atomics.
817814
bool enableAtomicExpand() const override;

‎llvm/test/CodeGen/ARM/memcpy-ldm-stm.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -36,10 +36,10 @@ entry:
3636
; CHECKV6-NEXT: ldr [[SB:r[0-7]]],
3737
; CHECKV6-NEXT: ldm{{(\.w)?}} [[LB]]!,
3838
; CHECKV6-NEXT: stm{{(\.w)?}} [[SB]]!,
39-
; CHECKV6-NEXT: ldrh{{(\.w)?}} {{.*}}, {{\[}}[[LB]]]
40-
; CHECKV6-NEXT: ldrb{{(\.w)?}} {{.*}}, {{\[}}[[LB]], #2]
41-
; CHECKV6-NEXT: strb{{(\.w)?}} {{.*}}, {{\[}}[[SB]], #2]
42-
; CHECKV6-NEXT: strh{{(\.w)?}} {{.*}}, {{\[}}[[SB]]]
39+
; CHECKV6-DAG: ldrh{{(\.w)?}} {{.*}}, {{\[}}[[LB]]]
40+
; CHECKV6-DAG: ldrb{{(\.w)?}} {{.*}}, {{\[}}[[LB]], #2]
41+
; CHECKV6-DAG: strb{{(\.w)?}} {{.*}}, {{\[}}[[SB]], #2]
42+
; CHECKV6-DAG: strh{{(\.w)?}} {{.*}}, {{\[}}[[SB]]]
4343
; CHECKV7: movt [[LB:[rl0-9]+]], :upper16:d
4444
; CHECKV7-NEXT: movt [[SB:[rl0-9]+]], :upper16:s
4545
; CHECKV7: ldr{{(\.w)?}} {{.*}}, {{\[}}[[LB]], #11]

‎llvm/test/CodeGen/ARM/thumb1_return_sequence.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -57,14 +57,14 @@ entry:
5757

5858
; Epilogue
5959
; --------
60-
; CHECK-V4T: ldr [[POP:r[4567]]], [sp, #16]
60+
; CHECK-V4T: ldr [[POP:r[4567]]], [sp, #12]
6161
; CHECK-V4T-NEXT: mov lr, [[POP]]
6262
; CHECK-V4T-NEXT: pop {[[SAVED]]}
6363
; CHECK-V4T-NEXT: add sp, #16
6464
; CHECK-V4T-NEXT: bx lr
6565
; CHECK-V5T: lsls r4
6666
; CHECK-V5T-NEXT: mov sp, r4
67-
; CHECK-V5T: ldr [[POP:r[4567]]], [sp, #16]
67+
; CHECK-V5T: ldr [[POP:r[4567]]], [sp, #12]
6868
; CHECK-V5T-NEXT: mov lr, [[POP]]
6969
; CHECK-V5T-NEXT: pop {[[SAVED]]}
7070
; CHECK-V5T-NEXT: add sp, #16

‎llvm/test/CodeGen/ARM/useaa.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,9 +7,9 @@
77

88
; CHECK-LABEL: test
99
; GENERIC: ldr
10-
; GENERIC: str
1110
; GENERIC: ldr
1211
; GENERIC: str
12+
; GENERIC: str
1313
; USEAA: ldr
1414
; USEAA: ldr
1515
; USEAA: str

‎llvm/test/CodeGen/ARM/va_arg.ll

Lines changed: 38 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,27 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
12
; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -pre-RA-sched=source | FileCheck %s
23
; Test that we correctly align elements when using va_arg
34

4-
; CHECK-LABEL: test1:
5-
; CHECK-NOT: bfc
6-
; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
7-
; CHECK: bic {{(r[0-9]+)|(lr)}}, [[REG]], #7
8-
; CHECK-NOT: bic
9-
105
define i64 @test1(i32 %i, ...) nounwind optsize {
6+
; CHECK-LABEL: test1:
7+
; CHECK: @ %bb.0: @ %entry
8+
; CHECK-NEXT: .pad #12
9+
; CHECK-NEXT: sub sp, sp, #12
10+
; CHECK-NEXT: .pad #4
11+
; CHECK-NEXT: sub sp, sp, #4
12+
; CHECK-NEXT: add r0, sp, #4
13+
; CHECK-NEXT: stmib sp, {r1, r2, r3}
14+
; CHECK-NEXT: add r0, r0, #7
15+
; CHECK-NEXT: bic r1, r0, #7
16+
; CHECK-NEXT: orr r2, r1, #4
17+
; CHECK-NEXT: str r2, [sp]
18+
; CHECK-NEXT: ldr r0, [r1]
19+
; CHECK-NEXT: add r2, r2, #4
20+
; CHECK-NEXT: str r2, [sp]
21+
; CHECK-NEXT: ldr r1, [r1, #4]
22+
; CHECK-NEXT: add sp, sp, #4
23+
; CHECK-NEXT: add sp, sp, #12
24+
; CHECK-NEXT: bx lr
1125
entry:
1226
%g = alloca i8*, align 4
1327
%g1 = bitcast i8** %g to i8*
@@ -17,14 +31,25 @@ entry:
1731
ret i64 %0
1832
}
1933

20-
; CHECK-LABEL: test2:
21-
; CHECK-NOT: bfc
22-
; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
23-
; CHECK: bic {{(r[0-9]+)|(lr)}}, [[REG]], #7
24-
; CHECK-NOT: bic
25-
; CHECK: bx lr
26-
2734
define double @test2(i32 %a, i32* %b, ...) nounwind optsize {
35+
; CHECK-LABEL: test2:
36+
; CHECK: @ %bb.0: @ %entry
37+
; CHECK-NEXT: .pad #8
38+
; CHECK-NEXT: sub sp, sp, #8
39+
; CHECK-NEXT: .pad #4
40+
; CHECK-NEXT: sub sp, sp, #4
41+
; CHECK-NEXT: add r0, sp, #4
42+
; CHECK-NEXT: stmib sp, {r2, r3}
43+
; CHECK-NEXT: add r0, r0, #11
44+
; CHECK-NEXT: bic r0, r0, #3
45+
; CHECK-NEXT: str r2, [r1]
46+
; CHECK-NEXT: add r1, r0, #8
47+
; CHECK-NEXT: str r1, [sp]
48+
; CHECK-NEXT: vldr d16, [r0]
49+
; CHECK-NEXT: vmov r0, r1, d16
50+
; CHECK-NEXT: add sp, sp, #4
51+
; CHECK-NEXT: add sp, sp, #8
52+
; CHECK-NEXT: bx lr
2853
entry:
2954
%ap = alloca i8*, align 4 ; <i8**> [#uses=3]
3055
%ap1 = bitcast i8** %ap to i8* ; <i8*> [#uses=2]

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