[IndVarSimplify] Add additional tests using isImpliedViaMerge.

Author: fhahn

llvm/test/Transforms/IndVarSimplify/eliminate-exit.ll

@@ -436,3 +436,58 @@ exit:
 }
 
 declare void @side_effect()
+
+; The exit condition %outer.cond.1 depends on a phi in %inner. Make sure we do
+; not incorrectly determine %x.lcssa <= -1.
+define i32 @exit_cond_depends_on_inner_loop() {
+; CHECK-LABEL: @exit_cond_depends_on_inner_loop(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br label [[OUTER_HEADER:%.*]]
+; CHECK:       outer.header:
+; CHECK-NEXT:    [[IV_OUTER:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_OUTER_NEXT:%.*]], [[OUTER_LATCH:%.*]] ]
+; CHECK-NEXT:    br label [[INNER:%.*]]
+; CHECK:       inner:
+; CHECK-NEXT:    [[X:%.*]] = phi i32 [ -1, [[OUTER_HEADER]] ], [ [[CALL:%.*]], [[INNER]] ]
+; CHECK-NEXT:    [[CALL]] = call i32 @match()
+; CHECK-NEXT:    [[INNER_COND:%.*]] = icmp sgt i32 [[CALL]], -1
+; CHECK-NEXT:    br i1 [[INNER_COND]], label [[INNER]], label [[OUTER_EXITING_1:%.*]]
+; CHECK:       outer.exiting.1:
+; CHECK-NEXT:    [[X_LCSSA:%.*]] = phi i32 [ [[X]], [[INNER]] ]
+; CHECK-NEXT:    br i1 false, label [[EXIT:%.*]], label [[OUTER_LATCH]]
+; CHECK:       outer.latch:
+; CHECK-NEXT:    [[IV_OUTER_NEXT]] = add nuw nsw i32 [[IV_OUTER]], 1
+; CHECK-NEXT:    [[OUTER_COND_2:%.*]] = icmp ult i32 [[IV_OUTER]], 100
+; CHECK-NEXT:    br i1 [[OUTER_COND_2]], label [[OUTER_HEADER]], label [[EXIT]]
+; CHECK:       exit:
+; CHECK-NEXT:    [[X_RES:%.*]] = phi i32 [ [[X_LCSSA]], [[OUTER_EXITING_1]] ], [ -1, [[OUTER_LATCH]] ]
+; CHECK-NEXT:    ret i32 [[X_RES]]
+;
+entry:
+  br label %outer.header
+
+outer.header:
+  %iv.outer = phi i32 [ 0, %entry ], [ %iv.outer.next , %outer.latch ]
+  br label %inner
+
+inner:
+  %x = phi i32 [ -1, %outer.header ], [ %call, %inner ]
+  %call = call i32 @match()
+  %inner.cond = icmp sgt i32 %call, -1
+  br i1 %inner.cond, label %inner, label %outer.exiting.1
+
+outer.exiting.1:
+  %x.lcssa = phi i32 [ %x, %inner ]
+  %outer.cond.1 = icmp sgt i32 %x.lcssa, -1
+  br i1 %outer.cond.1, label %exit, label %outer.latch
+
+outer.latch:
+  %iv.outer.next = add nuw nsw i32 %iv.outer, 1
+  %outer.cond.2 = icmp ult i32 %iv.outer, 100
+  br i1 %outer.cond.2, label %outer.header, label %exit
+
+exit:
+  %x.res = phi i32 [ %x.lcssa, %outer.exiting.1 ], [ -1, %outer.latch ]
+  ret i32 %x.res
+}
+
+declare i32 @match()

llvm/test/Transforms/IndVarSimplify/promote-iv-to-eliminate-casts.ll

@@ -373,4 +373,66 @@ loop:
   br i1 %loopcond, label %loopexit, label %loop
 }
 
+define void @promote_latch_condition_decrementing_loop_05(i32* %p, i32* %a, i1 %cond) {
+; CHECK-LABEL: @promote_latch_condition_decrementing_loop_05(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[LEN:%.*]] = load i32, i32* [[P:%.*]], align 4, [[RNG0]]
+; CHECK-NEXT:    br i1 [[COND:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
+; CHECK:       if.true:
+; CHECK-NEXT:    br label [[MERGE:%.*]]
+; CHECK:       if.false:
+; CHECK-NEXT:    [[LEN_MINUS_1:%.*]] = add nsw i32 [[LEN]], -1
+; CHECK-NEXT:    br label [[MERGE]]
+; CHECK:       merge:
+; CHECK-NEXT:    [[IV_START:%.*]] = phi i32 [ [[LEN]], [[IF_TRUE]] ], [ [[LEN_MINUS_1]], [[IF_FALSE]] ]
+; CHECK-NEXT:    [[ZERO_CHECK:%.*]] = icmp eq i32 [[LEN]], 0
+; CHECK-NEXT:    br i1 [[ZERO_CHECK]], label [[LOOPEXIT:%.*]], label [[PREHEADER:%.*]]
+; CHECK:       preheader:
+; CHECK-NEXT:    [[TMP0:%.*]] = zext i32 [[IV_START]] to i64
+; CHECK-NEXT:    br label [[LOOP:%.*]]
+; CHECK:       loopexit.loopexit:
+; CHECK-NEXT:    br label [[LOOPEXIT]]
+; CHECK:       loopexit:
+; CHECK-NEXT:    ret void
+; CHECK:       loop:
+; CHECK-NEXT:    [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ], [ [[TMP0]], [[PREHEADER]] ]
+; CHECK-NEXT:    [[EL:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[INDVARS_IV]]
+; CHECK-NEXT:    store atomic i32 0, i32* [[EL]] unordered, align 4
+; CHECK-NEXT:    [[LOOPCOND:%.*]] = icmp slt i64 [[INDVARS_IV]], 1
+; CHECK-NEXT:    [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], -1
+; CHECK-NEXT:    br i1 [[LOOPCOND]], label [[LOOPEXIT_LOOPEXIT:%.*]], label [[LOOP]]
+;
+
+entry:
+  %len = load i32, i32* %p, align 4, !range !0
+  br i1 %cond, label %if.true, label %if.false
+
+if.true:
+  br label %merge
+
+if.false:
+  %len.minus.1 = add nsw i32 %len, -1
+  br label %merge
+
+merge:
+  %iv_start = phi i32 [ %len, %if.true ], [%len.minus.1, %if.false ]
+  %zero_check = icmp eq i32 %len, 0
+  br i1 %zero_check, label %loopexit, label %preheader
+
+preheader:
+  br label %loop
+
+loopexit:
+  ret void
+
+loop:
+  %iv = phi i32 [ %iv.next, %loop ], [ %iv_start, %preheader ]
+  %iv.wide = zext i32 %iv to i64
+  %el = getelementptr inbounds i32, i32* %a, i64 %iv.wide
+  store atomic i32 0, i32* %el unordered, align 4
+  %iv.next = add nsw i32 %iv, -1
+  %loopcond = icmp slt i32 %iv, 1
+  br i1 %loopcond, label %loopexit, label %loop
+}
+
 !0 = !{i32 0, i32 2147483647}